Home
last modified time | relevance | path

Searched refs:PixelClockBackEnd (Results 1 – 6 of 6) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddisplay_mode_vba_20.c1787 mode_lib->vba.PixelClockBackEnd[k] / 6 in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1794 mode_lib->vba.PixelClockBackEnd[k] / 3 in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1839 / mode_lib->vba.PixelClockBackEnd[k]; in dml20_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4060 dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24, in dml20_ModeSupportAndSystemConfigurationFull()
4076 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20_ModeSupportAndSystemConfigurationFull()
4083 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20_ModeSupportAndSystemConfigurationFull()
4105 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20_ModeSupportAndSystemConfigurationFull()
4112 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20_ModeSupportAndSystemConfigurationFull()
4136 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20_ModeSupportAndSystemConfigurationFull()
4143 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20_ModeSupportAndSystemConfigurationFull()
[all …]
H A Ddisplay_mode_vba_20v2.c1823 mode_lib->vba.PixelClockBackEnd[k] / 6 in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1830 mode_lib->vba.PixelClockBackEnd[k] / 3 in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1875 / mode_lib->vba.PixelClockBackEnd[k]; in dml20v2_DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4140 dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24, in dml20v2_ModeSupportAndSystemConfigurationFull()
4156 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20v2_ModeSupportAndSystemConfigurationFull()
4163 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20v2_ModeSupportAndSystemConfigurationFull()
4185 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20v2_ModeSupportAndSystemConfigurationFull()
4192 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20v2_ModeSupportAndSystemConfigurationFull()
4216 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20v2_ModeSupportAndSystemConfigurationFull()
4223 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml20v2_ModeSupportAndSystemConfigurationFull()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dml/dcn21/
H A Ddisplay_mode_vba_21.c1774 mode_lib->vba.PixelClockBackEnd[k] / 6 in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1781 mode_lib->vba.PixelClockBackEnd[k] / 3 in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1826 / mode_lib->vba.PixelClockBackEnd[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4141 dml_min(600.0, mode_lib->vba.PHYCLKPerState[i]) / mode_lib->vba.PixelClockBackEnd[k] * 24, in dml21_ModeSupportAndSystemConfigurationFull()
4158 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml21_ModeSupportAndSystemConfigurationFull()
4166 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml21_ModeSupportAndSystemConfigurationFull()
4189 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml21_ModeSupportAndSystemConfigurationFull()
4197 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml21_ModeSupportAndSystemConfigurationFull()
4222 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml21_ModeSupportAndSystemConfigurationFull()
4230 * mode_lib->vba.OutputLinkDPLanes[k] / mode_lib->vba.PixelClockBackEnd[k] * 8.0, in dml21_ModeSupportAndSystemConfigurationFull()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddisplay_mode_vba_30.c2186 v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 12 in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2189 v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 6 in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2192 v->DSCCLK_calculated[k] = v->PixelClockBackEnd[k] / 3 in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2227 v->DSCDelay[k] = v->DSCDelay[k] * v->PixelClock[k] / v->PixelClockBackEnd[k]; in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4131 if (v->PixelClockBackEnd[k] > 3200) { in dml30_ModeSupportAndSystemConfigurationFull()
4132 v->NumberOfDSCSlices[k] = dml_ceil(v->PixelClockBackEnd[k] / 400.0, 4.0); in dml30_ModeSupportAndSystemConfigurationFull()
4133 } else if (v->PixelClockBackEnd[k] > 1360) { in dml30_ModeSupportAndSystemConfigurationFull()
4135 } else if (v->PixelClockBackEnd[k] > 680) { in dml30_ModeSupportAndSystemConfigurationFull()
4137 } else if (v->PixelClockBackEnd[k] > 340) { in dml30_ModeSupportAndSystemConfigurationFull()
4160 v->PixelClockBackEnd[k], in dml30_ModeSupportAndSystemConfigurationFull()
[all …]
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/display/dc/dml/
H A Ddisplay_mode_vba.c524 mode_lib->vba.PixelClockBackEnd[mode_lib->vba.NumberOfActivePlanes] = dst->pixel_rate_mhz; in fetch_pipe_params()
809 mode_lib->vba.PixelClock[k] = 2 * mode_lib->vba.PixelClockBackEnd[k]; in PixelClockAdjustmentForProgressiveToInterlaceUnit()
H A Ddisplay_mode_vba.h308 double PixelClockBackEnd[DC__NUM_DPP__MAX]; member