Searched refs:PP_SMU_RESULT_OK (Results 1 – 5 of 5) sorted by relevance
670 return PP_SMU_RESULT_OK; in pp_nv_set_wm_ranges()686 return PP_SMU_RESULT_OK; in pp_nv_set_pme_wa_enable()702 return PP_SMU_RESULT_OK; in pp_nv_set_display_count()719 return PP_SMU_RESULT_OK; in pp_nv_set_min_deep_sleep_dcfclk()742 return PP_SMU_RESULT_OK; in pp_nv_set_hard_min_dcefclk_by_freq()765 return PP_SMU_RESULT_OK; in pp_nv_set_hard_min_uclk_by_freq()778 return PP_SMU_RESULT_OK; in pp_nv_set_pstate_handshake_support()813 return PP_SMU_RESULT_OK; in pp_nv_set_voltage_by_freq()830 return PP_SMU_RESULT_OK; in pp_nv_get_maximum_sustainable_clocks()850 return PP_SMU_RESULT_OK; in pp_nv_get_uclk_dpm_states()[all …]
62 PP_SMU_RESULT_OK = 1, enumerator
919 if (status == PP_SMU_RESULT_OK && in rn_clk_mgr_construct()
1482 return PP_SMU_RESULT_OK; in dummy_set_wm_ranges()1489 return PP_SMU_RESULT_OK; in dummy_get_dpm_clock_table()
3746 uclk_states_available = (status == PP_SMU_RESULT_OK);3756 clock_limits_available = (status == PP_SMU_RESULT_OK);