Searched refs:PHY_LANES (Results 1 – 4 of 4) sorted by relevance
| /OK3568_Linux_fs/u-boot/drivers/video/drm/ |
| H A D | dw-dp.c | 122 #define PHY_LANES GENMASK(7, 6) macro
637 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_LANES, in dw_dp_link_configure()
638 FIELD_PREP(PHY_LANES, link->lanes / 2)); in dw_dp_link_configure()
1012 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_LANES, in dw_dp_set_phy_default_config()
1013 FIELD_PREP(PHY_LANES, link->lanes / 2)); in dw_dp_set_phy_default_config()
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| H A D | dw_mipi_dsi2.c | 75 #define PHY_LANES(x) UPDATE(x - 1, 5, 4) macro
946 val |= PPI_WIDTH(PPI_WIDTH_16_BITS) | PHY_LANES(dsi2->lanes); in dw_mipi_dsi2_phy_mode_cfg()
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/rockchip/ |
| H A D | dw-mipi-dsi2-rockchip.c | 84 #define PHY_LANES(x) UPDATE(x - 1, 5, 4) macro
586 val |= PPI_WIDTH(PPI_WIDTH_16_BITS) | PHY_LANES(dsi2->lanes); in dw_mipi_dsi2_phy_mode_cfg()
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| H A D | dw-dp.c | 136 #define PHY_LANES GENMASK(7, 6) macro
1559 regmap_update_bits(dp->regmap, DPTX_PHYIF_CTRL, PHY_LANES, in dw_dp_phy_configure()
1560 FIELD_PREP(PHY_LANES, lanes / 2)); in dw_dp_phy_configure()
2780 switch (FIELD_GET(PHY_LANES, value)) { in _dw_dp_loader_protect()
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