Searched refs:PHY_DP_MODE_CTL (Results 1 – 1 of 1) sorted by relevance
305 #define PHY_DP_MODE_CTL (0xc008 << 2) macro662 reg = readl(tcphy->base + PHY_DP_MODE_CTL); in tcphy_dp_set_power_state()665 writel(reg, tcphy->base + PHY_DP_MODE_CTL); in tcphy_dp_set_power_state()667 ret = readl_poll_timeout(tcphy->base + PHY_DP_MODE_CTL, in tcphy_dp_set_power_state()927 reg = readl(tcphy->base + PHY_DP_MODE_CTL); in tcphy_dp_set_lane_count()945 writel(reg, tcphy->base + PHY_DP_MODE_CTL); in tcphy_dp_set_lane_count()1307 val = readl(tcphy->base + PHY_DP_MODE_CTL); in tcphy_phy_init()1310 writel(val, tcphy->base + PHY_DP_MODE_CTL); in tcphy_phy_init()1528 ret = readx_poll_timeout(readl, tcphy->base + PHY_DP_MODE_CTL, in rockchip_dp_phy_power_on()