Searched refs:PCI_L1SS_CTL1_L1_2_MASK (Results 1 – 3 of 3) sorted by relevance
227 pl1_2_enables = pctl1 & PCI_L1SS_CTL1_L1_2_MASK; in aspm_calc_l1ss_info()228 cl1_2_enables = cctl1 & PCI_L1SS_CTL1_L1_2_MASK; in aspm_calc_l1ss_info()232 PCI_L1SS_CTL1_L1_2_MASK, 0); in aspm_calc_l1ss_info()234 PCI_L1SS_CTL1_L1_2_MASK, 0); in aspm_calc_l1ss_info()
509 pl1_2_enables = pctl1 & PCI_L1SS_CTL1_L1_2_MASK; in aspm_calc_l1ss_info()510 cl1_2_enables = cctl1 & PCI_L1SS_CTL1_L1_2_MASK; in aspm_calc_l1ss_info()514 PCI_L1SS_CTL1_L1_2_MASK, 0); in aspm_calc_l1ss_info()516 PCI_L1SS_CTL1_L1_2_MASK, 0); in aspm_calc_l1ss_info()
1075 #define PCI_L1SS_CTL1_L1_2_MASK 0x00000005 macro