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Searched refs:PCIE_CNTL2__SLV_MEM_LS_EN_MASK (Results 1 – 14 of 14) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/
H A Dnbio_v6_1.c180 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | in nbio_v6_1_update_medium_grain_light_sleep()
184 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | in nbio_v6_1_update_medium_grain_light_sleep()
205 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) in nbio_v6_1_get_clockgating_state()
H A Dnbio_v7_0.c203 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | in nbio_v7_0_update_medium_grain_light_sleep()
207 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | in nbio_v7_0_update_medium_grain_light_sleep()
228 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) in nbio_v7_0_get_clockgating_state()
H A Dnbio_v2_3.c239 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | in nbio_v2_3_update_medium_grain_light_sleep()
243 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | in nbio_v2_3_update_medium_grain_light_sleep()
264 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) in nbio_v2_3_get_clockgating_state()
H A Dnbio_v7_4.c209 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK | in nbio_v7_4_update_medium_grain_light_sleep()
213 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | in nbio_v7_4_update_medium_grain_light_sleep()
234 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) in nbio_v7_4_get_clockgating_state()
H A Dvi.c1416 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK | in vi_update_bif_medium_grain_light_sleep()
1420 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK | in vi_update_bif_medium_grain_light_sleep()
1670 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK) in vi_common_get_clockgating_state()
H A Dcik.c1796 data |= PCIE_CNTL2__SLV_MEM_LS_EN_MASK | in cik_program_aspm()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/bif/
H A Dbif_3_0_sh_mask.h6646 #define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x00010000L macro
H A Dbif_4_1_sh_mask.h2059 #define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x10000 macro
H A Dbif_5_0_sh_mask.h2631 #define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x10000 macro
H A Dbif_5_1_sh_mask.h3013 #define PCIE_CNTL2__SLV_MEM_LS_EN_MASK 0x10000 macro
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_4_sh_mask.h43498 #define PCIE_CNTL2__SLV_MEM_LS_EN_MASK … macro
H A Dnbio_2_3_sh_mask.h54853 #define PCIE_CNTL2__SLV_MEM_LS_EN_MASK … macro
H A Dnbio_7_0_sh_mask.h74167 #define PCIE_CNTL2__SLV_MEM_LS_EN_MASK … macro
H A Dnbio_6_1_sh_mask.h38794 #define PCIE_CNTL2__SLV_MEM_LS_EN_MASK … macro