Searched refs:PADS_PLL_CTL_RST_B4SM (Results 1 – 2 of 2) sorted by relevance
150 #define PADS_PLL_CTL_RST_B4SM (0x1 << 1) macro697 value &= ~PADS_PLL_CTL_RST_B4SM; in tegra_pcie_phy_enable()704 value |= PADS_PLL_CTL_RST_B4SM; in tegra_pcie_phy_enable()
254 #define PADS_PLL_CTL_RST_B4SM (1 << 1) macro955 value &= ~PADS_PLL_CTL_RST_B4SM; in tegra_pcie_phy_enable()962 value |= PADS_PLL_CTL_RST_B4SM; in tegra_pcie_phy_enable()1002 value &= ~PADS_PLL_CTL_RST_B4SM; in tegra_pcie_phy_disable()