1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * os02g10 driver
4 *
5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
6 *
7 * V0.0X01.0X00 first version.
8 * V0.0X01.0X01 update init setting.
9 * V0.0X01.0X02 fix set flip/mirror failed bug and fix wrong vts_def value.
10 */
11
12 #include <linux/clk.h>
13 #include <linux/device.h>
14 #include <linux/delay.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/i2c.h>
17 #include <linux/module.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/sysfs.h>
21 #include <linux/slab.h>
22 #include <linux/version.h>
23 #include <linux/rk-camera-module.h>
24 #include <media/media-entity.h>
25 #include <media/v4l2-async.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-subdev.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/rk-preisp.h>
30 #include "../platform/rockchip/isp/rkisp_tb_helper.h"
31
32 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x02)
33
34 #ifndef V4L2_CID_DIGITAL_GAIN
35 #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
36 #endif
37
38 #define OS02G10_CHIP_ID 0x5602
39 #define OS02G10_REG_CHIP_ID_H 0x02
40 #define OS02G10_REG_CHIP_ID_L 0x03
41
42 #define OS02G10_XVCLK_FREQ 24000000
43 #define BITS_PER_SAMPLE 10
44 #define MIPI_FREQ_360M 360000000
45 #define OS02G10_LANES 2
46 #define PIXEL_RATE_WITH_360M (MIPI_FREQ_360M * OS02G10_LANES * 2 / BITS_PER_SAMPLE)
47
48 #define OS02G10_REG_PAGE_SELECT 0xfd
49
50 #define OS02G10_REG_EXP_H 0x03
51 #define OS02G10_REG_EXP_L 0x04
52 #define OS02G10_EXPOSURE_MIN 4
53 #define OS02G10_EXPOSURE_STEP 1
54
55 #define OS02G10_REG_AGAIN 0x24
56 #define OS02G10_REG_DGAIN_H 0x37
57 #define OS02G10_REG_DGAIN_L 0x39
58 #define OS02G10_GAIN_MIN 0x10
59 #define OS02G10_GAIN_MAX 0x2000
60 #define OS02G10_GAIN_STEP 1
61 #define OS02G10_GAIN_DEFAULT 0x10
62
63 #define OS02G10_REG_HTS_H 0x41
64 #define OS02G10_REG_HTS_L 0x42
65 #define OS02G10_REG_VTS_H 0x4e
66 #define OS02G10_REG_VTS_L 0x4f
67
68 #define OS02G10_REG_VBLANK_H 0x05
69 #define OS02G10_REG_VBLANK_L 0x06
70
71 #define OS02G10_VTS_MAX 0xffff
72 #define OS02G10_REG_RESTART 0x01
73
74 #define OS02G10_REG_CTRL_MODE 0xb1
75 #define OS02G10_MODE_SW_STANDBY 0x0
76 #define OS02G10_MODE_STREAMING 0x03
77
78 #define OS02G10_REG_SOFTWARE_RESET 0xfc
79 #define OS02G10_SOFTWARE_RESET_VAL 0x1
80
81 #define OS02G10_FLIP_REG 0x3f
82 #define MIRROR_BIT_MASK BIT(0)
83 #define FLIP_BIT_MASK BIT(1)
84 #define OS02G10_REG_BAYER_ORDER 0x5e
85
86 #define OS02G10_NAME "os02g10"
87
88 #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
89 #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
90 #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
91
92 #define REG_NULL 0xFF
93
94 #define SENSOR_ID(_msb, _lsb) ((_msb) << 8 | (_lsb))
95
96 static const char * const OS02G10_supply_names[] = {
97 "avdd", /* Analog power */
98 "dovdd", /* Digital I/O power */
99 "dvdd", /* Digital core power */
100 };
101
102 #define OS02G10_NUM_SUPPLIES ARRAY_SIZE(OS02G10_supply_names)
103
104 struct regval {
105 u8 addr;
106 u8 val;
107 };
108
109 struct os02g10_mode {
110 u32 bus_fmt;
111 u32 width;
112 u32 height;
113 struct v4l2_fract max_fps;
114 u32 hts_def;
115 u32 vts_def;
116 u32 exp_def;
117 const struct regval *reg_list;
118 u32 hdr_mode;
119 u32 vc[PAD_MAX];
120 };
121
122 struct os02g10 {
123 struct i2c_client *client;
124 struct clk *xvclk;
125 struct gpio_desc *reset_gpio;
126 struct gpio_desc *pwdn_gpio;
127 struct regulator_bulk_data supplies[OS02G10_NUM_SUPPLIES];
128 struct pinctrl *pinctrl;
129 struct pinctrl_state *pins_default;
130 struct pinctrl_state *pins_sleep;
131 struct v4l2_subdev subdev;
132 struct media_pad pad;
133 struct v4l2_ctrl_handler ctrl_handler;
134 struct v4l2_ctrl *exposure;
135 struct v4l2_ctrl *anal_gain;
136 struct v4l2_ctrl *digi_gain;
137 struct v4l2_ctrl *hblank;
138 struct v4l2_ctrl *vblank;
139 struct v4l2_ctrl *pixel_rate;
140 struct v4l2_ctrl *link_freq;
141 struct mutex mutex;
142 bool streaming;
143 bool power_on;
144 const struct os02g10_mode *cur_mode;
145 u32 cfg_num;
146 u32 module_index;
147 const char *module_facing;
148 const char *module_name;
149 const char *len_name;
150 bool has_init_exp;
151 struct preisp_hdrae_exp_s init_hdrae_exp;
152 u8 flip;
153 };
154
155 #define to_os02g10(sd) container_of(sd, struct os02g10, subdev)
156
157 static const struct regval os02g10_linear10bit_1920x1080_regs[] = {
158 {0xfd, 0x00},
159 {0xfd, 0x00},
160 {0x30, 0x0a},
161 {0x35, 0x04},
162 {0x38, 0x11},
163 {0x41, 0x06},
164 {0x44, 0x20},
165 {0xfd, 0x01},
166 {0x03, 0x04},
167 {0x04, 0x4c},
168 {0x06, 0x00},
169 {0x24, 0x30},
170 {0x01, 0x01},
171 {0x19, 0x50},
172 {0x1a, 0x0c},
173 {0x1b, 0x0d},
174 {0x1c, 0x00},
175 {0x1d, 0x75},
176 {0x1e, 0x52},
177 {0x22, 0x14},
178 {0x25, 0x44},
179 {0x26, 0x0f},
180 {0x3c, 0xca},
181 {0x3d, 0x4a},
182 {0x40, 0x0f},
183 {0x43, 0x38},
184 {0x46, 0x00},
185 {0x47, 0x00},
186 {0x49, 0x32},
187 {0x50, 0x01},
188 {0x51, 0x28},
189 {0x52, 0x20},
190 {0x53, 0x03},
191 {0x57, 0x16},
192 {0x59, 0x01},
193 {0x5a, 0x01},
194 {0x5d, 0x04},
195 {0x6a, 0x04},
196 {0x6b, 0x03},
197 {0x6e, 0x28},
198 {0x71, 0xbe},
199 {0x72, 0x06},
200 {0x73, 0x38},
201 {0x74, 0x06},
202 {0x79, 0x00},
203 {0x7a, 0xb2},
204 {0x7b, 0x10},
205 {0x8f, 0x80},
206 {0x91, 0x38},
207 {0x92, 0x0a},
208 {0x9d, 0x03},
209 {0x9e, 0x55},
210 {0xb8, 0x70},
211 {0xb9, 0x70},
212 {0xba, 0x70},
213 {0xbb, 0x70},
214 {0xbc, 0x00},
215 {0xc0, 0x00},
216 {0xc1, 0x00},
217 {0xc2, 0x00},
218 {0xc3, 0x00},
219 {0xc4, 0x6e},
220 {0xc5, 0x6e},
221 {0xc6, 0x6b},
222 {0xc7, 0x6b},
223 {0xcc, 0x11},
224 {0xcd, 0xe0},
225 {0xd0, 0x1b},
226 {0xd2, 0x76},
227 {0xd3, 0x68},
228 {0xd4, 0x68},
229 {0xd5, 0x73},
230 {0xd6, 0x73},
231 {0xe8, 0x55},
232 {0xf0, 0x40},
233 {0xf1, 0x40},
234 {0xf2, 0x40},
235 {0xf3, 0x40},
236 {0xf4, 0x00},
237 {0xfa, 0x1c},
238 {0xfb, 0x33},
239 {0xfc, 0xff},
240 {0xfe, 0x01},
241 {0xfd, 0x03},
242 {0x03, 0x67},
243 {0x00, 0x59},
244 {0x04, 0x11},
245 {0x05, 0x04},
246 {0x06, 0x0c},
247 {0x07, 0x08},
248 {0x08, 0x08},
249 {0x09, 0x4f},
250 {0x0b, 0x08},
251 {0x0d, 0x26},
252 {0x0f, 0x00},
253 {0xfd, 0x02},
254 {0x34, 0xfe},
255 {0x5e, 0x22},
256 {0xa1, 0x06},
257 {0xa3, 0x38},
258 {0xa5, 0x02},
259 {0xa7, 0x80},
260 {0xfd, 0x01},
261 {0xa1, 0x05},
262 {0x94, 0x44},
263 {0x95, 0x44},
264 {0x96, 0x09},
265 {0x98, 0x44},
266 {0x9c, 0x0e},
267 {0xb1, 0x01},
268 {0xfd, 0x01},
269 {REG_NULL, 0x00},
270 };
271
272 /*
273 * The width and height must be configured to be
274 * the same as the current output resolution of the sensor.
275 * The input width of the isp needs to be 16 aligned.
276 * The input height of the isp needs to be 8 aligned.
277 * If the width or height does not meet the alignment rules,
278 * you can configure the cropping parameters with the following function to
279 * crop out the appropriate resolution.
280 * struct v4l2_subdev_pad_ops {
281 * .get_selection
282 * }
283 */
284 static const struct os02g10_mode supported_modes[] = {
285 {
286 .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
287 .width = 1920,
288 .height = 1080,
289 .max_fps = {
290 .numerator = 10000,
291 .denominator = 250000,
292 },
293 .exp_def = 0x044c,
294 .hts_def = 0x043a * 2,
295 .vts_def = 0x0516,
296 .reg_list = os02g10_linear10bit_1920x1080_regs,
297 .hdr_mode = NO_HDR,
298 .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
299 },
300 };
301
302 static const s64 link_freq_menu_items[] = {
303 MIPI_FREQ_360M,
304 };
305
306 /* sensor register write */
os02g10_write_reg(struct i2c_client * client,u8 reg,u8 val)307 static int os02g10_write_reg(struct i2c_client *client, u8 reg, u8 val)
308 {
309 struct i2c_msg msg;
310 u8 buf[2];
311 int ret;
312
313 buf[0] = reg & 0xFF;
314 buf[1] = val;
315
316 msg.addr = client->addr;
317 msg.flags = client->flags;
318 msg.buf = buf;
319 msg.len = sizeof(buf);
320
321 ret = i2c_transfer(client->adapter, &msg, 1);
322
323 if (ret >= 0)
324 return 0;
325
326 dev_err(&client->dev, "write reg(0x%x val:0x%x) failed !\n", reg, val);
327
328 return ret;
329 }
330
os02g10_write_array(struct i2c_client * client,const struct regval * regs)331 static int os02g10_write_array(struct i2c_client *client,
332 const struct regval *regs)
333 {
334 int i, ret = 0;
335
336 i = 0;
337 while (regs[i].addr != REG_NULL) {
338 ret = os02g10_write_reg(client, regs[i].addr, regs[i].val);
339 if (ret) {
340 dev_err(&client->dev, "%s failed !\n", __func__);
341 break;
342 }
343 i++;
344 }
345
346 return ret;
347 }
348
349 /* sensor register read */
os02g10_read_reg(struct i2c_client * client,u8 reg,u8 * val)350 static int os02g10_read_reg(struct i2c_client *client, u8 reg, u8 *val)
351 {
352 struct i2c_msg msg[2];
353 u8 buf[1];
354 int ret;
355
356 buf[0] = reg & 0xFF;
357
358 msg[0].addr = client->addr;
359 msg[0].flags = client->flags;
360 msg[0].buf = buf;
361 msg[0].len = sizeof(buf);
362
363 msg[1].addr = client->addr;
364 msg[1].flags = client->flags | I2C_M_RD;
365 msg[1].buf = buf;
366 msg[1].len = 1;
367
368 ret = i2c_transfer(client->adapter, msg, 2);
369 if (ret >= 0) {
370 *val = buf[0];
371 return 0;
372 }
373
374 dev_err(&client->dev,
375 "os02g10 read reg(0x%x val:0x%x) failed !\n", reg, *val);
376
377 return ret;
378 }
379
os02g10_get_reso_dist(const struct os02g10_mode * mode,struct v4l2_mbus_framefmt * framefmt)380 static int os02g10_get_reso_dist(const struct os02g10_mode *mode,
381 struct v4l2_mbus_framefmt *framefmt)
382 {
383 return abs(mode->width - framefmt->width) +
384 abs(mode->height - framefmt->height);
385 }
386
387 static const struct os02g10_mode *
os02g10_find_best_fit(struct os02g10 * os02g10,struct v4l2_subdev_format * fmt)388 os02g10_find_best_fit(struct os02g10 *os02g10, struct v4l2_subdev_format *fmt)
389 {
390 struct v4l2_mbus_framefmt *framefmt = &fmt->format;
391 int dist;
392 int cur_best_fit = 0;
393 int cur_best_fit_dist = -1;
394 unsigned int i;
395
396 for (i = 0; i < os02g10->cfg_num; i++) {
397 dist = os02g10_get_reso_dist(&supported_modes[i], framefmt);
398 if ((cur_best_fit_dist == -1 || dist <= cur_best_fit_dist) &&
399 (supported_modes[i].bus_fmt == framefmt->code)) {
400 cur_best_fit_dist = dist;
401 cur_best_fit = i;
402 }
403 }
404
405 return &supported_modes[cur_best_fit];
406 }
407
os02g10_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)408 static int os02g10_set_fmt(struct v4l2_subdev *sd,
409 struct v4l2_subdev_pad_config *cfg,
410 struct v4l2_subdev_format *fmt)
411 {
412 struct os02g10 *os02g10 = to_os02g10(sd);
413 const struct os02g10_mode *mode;
414 s64 h_blank, vblank_def;
415 u64 dst_link_freq = 0;
416 u64 dst_pixel_rate = 0;
417
418 mutex_lock(&os02g10->mutex);
419
420 mode = os02g10_find_best_fit(os02g10, fmt);
421 fmt->format.code = mode->bus_fmt;
422 fmt->format.width = mode->width;
423 fmt->format.height = mode->height;
424 fmt->format.field = V4L2_FIELD_NONE;
425 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
426 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
427 *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
428 #else
429 mutex_unlock(&os02g10->mutex);
430 return -ENOTTY;
431 #endif
432 } else {
433 os02g10->cur_mode = mode;
434 h_blank = mode->hts_def - mode->width;
435 __v4l2_ctrl_modify_range(os02g10->hblank, h_blank,
436 h_blank, 1, h_blank);
437
438 vblank_def = mode->vts_def - mode->height;
439 __v4l2_ctrl_modify_range(os02g10->vblank, vblank_def,
440 OS02G10_VTS_MAX - mode->height,
441 1, vblank_def);
442 if (mode->hdr_mode == NO_HDR) {
443 if (mode->bus_fmt == MEDIA_BUS_FMT_SBGGR10_1X10) {
444 dst_link_freq = 0;
445 dst_pixel_rate = PIXEL_RATE_WITH_360M;
446 }
447 }
448 __v4l2_ctrl_s_ctrl_int64(os02g10->pixel_rate,
449 dst_pixel_rate);
450 __v4l2_ctrl_s_ctrl(os02g10->link_freq,
451 dst_link_freq);
452 }
453
454 mutex_unlock(&os02g10->mutex);
455
456 return 0;
457 }
458
os02g10_get_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)459 static int os02g10_get_fmt(struct v4l2_subdev *sd,
460 struct v4l2_subdev_pad_config *cfg,
461 struct v4l2_subdev_format *fmt)
462 {
463 struct os02g10 *os02g10 = to_os02g10(sd);
464 const struct os02g10_mode *mode = os02g10->cur_mode;
465
466 mutex_lock(&os02g10->mutex);
467 if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
468 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
469 fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
470 #else
471 mutex_unlock(&os02g10->mutex);
472 return -ENOTTY;
473 #endif
474 } else {
475 fmt->format.width = mode->width;
476 fmt->format.height = mode->height;
477 fmt->format.code = mode->bus_fmt;
478 fmt->format.field = V4L2_FIELD_NONE;
479 if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
480 fmt->reserved[0] = mode->vc[fmt->pad];
481 else
482 fmt->reserved[0] = mode->vc[PAD0];
483 }
484 mutex_unlock(&os02g10->mutex);
485
486 return 0;
487 }
488
os02g10_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_mbus_code_enum * code)489 static int os02g10_enum_mbus_code(struct v4l2_subdev *sd,
490 struct v4l2_subdev_pad_config *cfg,
491 struct v4l2_subdev_mbus_code_enum *code)
492 {
493 struct os02g10 *os02g10 = to_os02g10(sd);
494
495 if (code->index != 0)
496 return -EINVAL;
497 code->code = os02g10->cur_mode->bus_fmt;
498
499 return 0;
500 }
501
os02g10_enum_frame_sizes(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_size_enum * fse)502 static int os02g10_enum_frame_sizes(struct v4l2_subdev *sd,
503 struct v4l2_subdev_pad_config *cfg,
504 struct v4l2_subdev_frame_size_enum *fse)
505 {
506 struct os02g10 *os02g10 = to_os02g10(sd);
507
508 if (fse->index >= os02g10->cfg_num)
509 return -EINVAL;
510
511 if (fse->code != supported_modes[fse->index].bus_fmt)
512 return -EINVAL;
513
514 fse->min_width = supported_modes[fse->index].width;
515 fse->max_width = supported_modes[fse->index].width;
516 fse->max_height = supported_modes[fse->index].height;
517 fse->min_height = supported_modes[fse->index].height;
518
519 return 0;
520 }
521
os02g10_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)522 static int os02g10_g_frame_interval(struct v4l2_subdev *sd,
523 struct v4l2_subdev_frame_interval *fi)
524 {
525 struct os02g10 *os02g10 = to_os02g10(sd);
526 const struct os02g10_mode *mode = os02g10->cur_mode;
527
528 fi->interval = mode->max_fps;
529
530 return 0;
531 }
532
os02g10_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_config * config)533 static int os02g10_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
534 struct v4l2_mbus_config *config)
535 {
536 struct os02g10 *os02g10 = to_os02g10(sd);
537 const struct os02g10_mode *mode = os02g10->cur_mode;
538 u32 val = 0;
539
540 if (mode->hdr_mode == NO_HDR)
541 val = 1 << (OS02G10_LANES - 1) |
542 V4L2_MBUS_CSI2_CHANNEL_0 |
543 V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
544
545 config->type = V4L2_MBUS_CSI2_DPHY;
546 config->flags = val;
547
548 return 0;
549 }
550
os02g10_get_module_inf(struct os02g10 * os02g10,struct rkmodule_inf * inf)551 static void os02g10_get_module_inf(struct os02g10 *os02g10,
552 struct rkmodule_inf *inf)
553 {
554 memset(inf, 0, sizeof(*inf));
555 strscpy(inf->base.sensor, OS02G10_NAME, sizeof(inf->base.sensor));
556 strscpy(inf->base.module, os02g10->module_name,
557 sizeof(inf->base.module));
558 strscpy(inf->base.lens, os02g10->len_name, sizeof(inf->base.lens));
559 }
560
os02g10_ioctl(struct v4l2_subdev * sd,unsigned int cmd,void * arg)561 static long os02g10_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
562 {
563 struct os02g10 *os02g10 = to_os02g10(sd);
564 struct rkmodule_hdr_cfg *hdr_cfg;
565 long ret = 0;
566 u32 stream = 0;
567
568 switch (cmd) {
569 case RKMODULE_GET_MODULE_INFO:
570 os02g10_get_module_inf(os02g10, (struct rkmodule_inf *)arg);
571 break;
572 case RKMODULE_SET_HDR_CFG:
573 hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
574 if (hdr_cfg->hdr_mode != 0)
575 ret = -1;
576 break;
577 case RKMODULE_GET_HDR_CFG:
578 hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
579 hdr_cfg->esp.mode = HDR_NORMAL_VC;
580 hdr_cfg->hdr_mode = os02g10->cur_mode->hdr_mode;
581 break;
582 case RKMODULE_SET_QUICK_STREAM:
583 stream = *((u32 *)arg);
584 if (stream)
585 ret = os02g10_write_reg(os02g10->client, OS02G10_REG_CTRL_MODE,
586 OS02G10_MODE_STREAMING);
587 else
588 ret = os02g10_write_reg(os02g10->client, OS02G10_REG_CTRL_MODE,
589 OS02G10_MODE_SW_STANDBY);
590 break;
591 default:
592 ret = -ENOIOCTLCMD;
593 break;
594 }
595
596 return ret;
597 }
598
599 #ifdef CONFIG_COMPAT
os02g10_compat_ioctl32(struct v4l2_subdev * sd,unsigned int cmd,unsigned long arg)600 static long os02g10_compat_ioctl32(struct v4l2_subdev *sd,
601 unsigned int cmd, unsigned long arg)
602 {
603 void __user *up = compat_ptr(arg);
604 struct rkmodule_inf *inf;
605 struct rkmodule_hdr_cfg *hdr;
606 long ret;
607 u32 stream = 0;
608
609 switch (cmd) {
610 case RKMODULE_GET_MODULE_INFO:
611 inf = kzalloc(sizeof(*inf), GFP_KERNEL);
612 if (!inf) {
613 ret = -ENOMEM;
614 return ret;
615 }
616
617 ret = os02g10_ioctl(sd, cmd, inf);
618 if (!ret) {
619 ret = copy_to_user(up, inf, sizeof(*inf));
620 if (ret)
621 ret = -EFAULT;
622 }
623 kfree(inf);
624 break;
625 case RKMODULE_GET_HDR_CFG:
626 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
627 if (!hdr) {
628 ret = -ENOMEM;
629 return ret;
630 }
631
632 ret = os02g10_ioctl(sd, cmd, hdr);
633 if (!ret) {
634 ret = copy_to_user(up, hdr, sizeof(*hdr));
635 if (ret)
636 ret = -EFAULT;
637 }
638 kfree(hdr);
639 break;
640 case RKMODULE_SET_HDR_CFG:
641 hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
642 if (!hdr) {
643 ret = -ENOMEM;
644 return ret;
645 }
646
647 if (copy_from_user(hdr, up, sizeof(*hdr)))
648 return -EFAULT;
649
650 ret = os02g10_ioctl(sd, cmd, hdr);
651 kfree(hdr);
652 break;
653 case RKMODULE_SET_QUICK_STREAM:
654 if (copy_from_user(&stream, up, sizeof(u32)))
655 return -EFAULT;
656
657 ret = os02g10_ioctl(sd, cmd, &stream);
658 break;
659 default:
660 ret = -ENOIOCTLCMD;
661 break;
662 }
663
664 return ret;
665 }
666 #endif
667
__os02g10_start_stream(struct os02g10 * os02g10)668 static int __os02g10_start_stream(struct os02g10 *os02g10)
669 {
670 int ret = 0;
671
672 ret |= os02g10_write_reg(os02g10->client, 0xfd, 0x00);
673 ret |= os02g10_write_reg(os02g10->client, 0x36, 0x01);
674 ret |= os02g10_write_reg(os02g10->client, 0xfd, 0x00);
675 ret |= os02g10_write_reg(os02g10->client, 0x36, 0x00);
676 ret |= os02g10_write_reg(os02g10->client, 0xfd, 0x00);
677
678 usleep_range(5000, 6000);
679
680 ret |= os02g10_write_array(os02g10->client, os02g10->cur_mode->reg_list);
681 if (ret)
682 return ret;
683
684 /* In case these controls are set before streaming */
685 ret = __v4l2_ctrl_handler_setup(&os02g10->ctrl_handler);
686 if (ret)
687 return ret;
688 if (os02g10->has_init_exp && os02g10->cur_mode->hdr_mode != NO_HDR) {
689 ret = os02g10_ioctl(&os02g10->subdev, PREISP_CMD_SET_HDRAE_EXP,
690 &os02g10->init_hdrae_exp);
691 if (ret) {
692 dev_err(&os02g10->client->dev,
693 "init exp fail in hdr mode\n");
694 return ret;
695 }
696 }
697 return os02g10_write_reg(os02g10->client, OS02G10_REG_CTRL_MODE, OS02G10_MODE_STREAMING);
698 }
699
__os02g10_stop_stream(struct os02g10 * os02g10)700 static int __os02g10_stop_stream(struct os02g10 *os02g10)
701 {
702 os02g10->has_init_exp = false;
703 return os02g10_write_reg(os02g10->client, OS02G10_REG_CTRL_MODE, OS02G10_MODE_SW_STANDBY);
704 }
705
os02g10_s_stream(struct v4l2_subdev * sd,int on)706 static int os02g10_s_stream(struct v4l2_subdev *sd, int on)
707 {
708 struct os02g10 *os02g10 = to_os02g10(sd);
709 struct i2c_client *client = os02g10->client;
710 int ret = 0;
711
712 mutex_lock(&os02g10->mutex);
713 on = !!on;
714 if (on == os02g10->streaming)
715 goto unlock_and_return;
716
717 if (on) {
718 ret = pm_runtime_get_sync(&client->dev);
719 if (ret < 0) {
720 pm_runtime_put_noidle(&client->dev);
721 goto unlock_and_return;
722 }
723
724 ret = __os02g10_start_stream(os02g10);
725 if (ret) {
726 v4l2_err(sd, "start stream failed while write regs\n");
727 pm_runtime_put(&client->dev);
728 goto unlock_and_return;
729 }
730 } else {
731 __os02g10_stop_stream(os02g10);
732 pm_runtime_put(&client->dev);
733 }
734
735 os02g10->streaming = on;
736
737 unlock_and_return:
738 mutex_unlock(&os02g10->mutex);
739
740 return ret;
741 }
742
os02g10_s_power(struct v4l2_subdev * sd,int on)743 static int os02g10_s_power(struct v4l2_subdev *sd, int on)
744 {
745 struct os02g10 *os02g10 = to_os02g10(sd);
746 struct i2c_client *client = os02g10->client;
747 int ret = 0;
748
749 mutex_lock(&os02g10->mutex);
750
751 /* If the power state is not modified - no work to do. */
752 if (os02g10->power_on == !!on)
753 goto unlock_and_return;
754
755 if (on) {
756 ret = pm_runtime_get_sync(&client->dev);
757 if (ret < 0) {
758 pm_runtime_put_noidle(&client->dev);
759 goto unlock_and_return;
760 }
761
762 ret |= os02g10_write_reg(os02g10->client,
763 OS02G10_REG_SOFTWARE_RESET,
764 OS02G10_SOFTWARE_RESET_VAL);
765 usleep_range(100, 200);
766
767 os02g10->power_on = true;
768 } else {
769 pm_runtime_put(&client->dev);
770 os02g10->power_on = false;
771 }
772
773 unlock_and_return:
774 mutex_unlock(&os02g10->mutex);
775
776 return ret;
777 }
778
__os02g10_power_on(struct os02g10 * os02g10)779 static int __os02g10_power_on(struct os02g10 *os02g10)
780 {
781 int ret;
782 struct device *dev = &os02g10->client->dev;
783
784 if (!IS_ERR_OR_NULL(os02g10->pins_default)) {
785 ret = pinctrl_select_state(os02g10->pinctrl,
786 os02g10->pins_default);
787 if (ret < 0)
788 dev_err(dev, "could not set pins\n");
789 }
790 ret = clk_set_rate(os02g10->xvclk, OS02G10_XVCLK_FREQ);
791 if (ret < 0)
792 dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
793 if (clk_get_rate(os02g10->xvclk) != OS02G10_XVCLK_FREQ)
794 dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
795 ret = clk_prepare_enable(os02g10->xvclk);
796 if (ret < 0) {
797 dev_err(dev, "Failed to enable xvclk\n");
798 return ret;
799 }
800
801 if (!IS_ERR(os02g10->pwdn_gpio))
802 gpiod_direction_output(os02g10->pwdn_gpio, 0);
803
804 if (!IS_ERR(os02g10->reset_gpio))
805 gpiod_direction_output(os02g10->reset_gpio, 0);
806
807 ret = regulator_bulk_enable(OS02G10_NUM_SUPPLIES, os02g10->supplies);
808 if (ret < 0) {
809 dev_err(dev, "Failed to enable regulators\n");
810 goto disable_clk;
811 }
812
813 /* From spec: delay from power stable to pwdn off: 5ms */
814 usleep_range(5000, 6000);
815 if (!IS_ERR(os02g10->pwdn_gpio))
816 gpiod_direction_output(os02g10->pwdn_gpio, 1);
817
818 /* From spec: delay from pwdn off to reset off */
819 usleep_range(4000, 5000);
820 if (!IS_ERR(os02g10->reset_gpio))
821 gpiod_direction_output(os02g10->reset_gpio, 1);
822
823 /* From spec: 5ms for SCCB initialization */
824 usleep_range(9000, 10000);
825 return 0;
826
827 disable_clk:
828 clk_disable_unprepare(os02g10->xvclk);
829
830 return ret;
831 }
832
__os02g10_power_off(struct os02g10 * os02g10)833 static void __os02g10_power_off(struct os02g10 *os02g10)
834 {
835 int ret;
836 struct device *dev = &os02g10->client->dev;
837
838 if (!IS_ERR(os02g10->pwdn_gpio))
839 gpiod_direction_output(os02g10->pwdn_gpio, 0);
840
841 clk_disable_unprepare(os02g10->xvclk);
842
843 if (!IS_ERR(os02g10->reset_gpio))
844 gpiod_direction_output(os02g10->reset_gpio, 0);
845 if (!IS_ERR_OR_NULL(os02g10->pins_sleep)) {
846 ret = pinctrl_select_state(os02g10->pinctrl,
847 os02g10->pins_sleep);
848 if (ret < 0)
849 dev_dbg(dev, "could not set pins\n");
850 }
851 regulator_bulk_disable(OS02G10_NUM_SUPPLIES, os02g10->supplies);
852 }
853
os02g10_runtime_resume(struct device * dev)854 static int os02g10_runtime_resume(struct device *dev)
855 {
856 struct i2c_client *client = to_i2c_client(dev);
857 struct v4l2_subdev *sd = i2c_get_clientdata(client);
858 struct os02g10 *os02g10 = to_os02g10(sd);
859
860 return __os02g10_power_on(os02g10);
861 }
862
os02g10_runtime_suspend(struct device * dev)863 static int os02g10_runtime_suspend(struct device *dev)
864 {
865 struct i2c_client *client = to_i2c_client(dev);
866 struct v4l2_subdev *sd = i2c_get_clientdata(client);
867 struct os02g10 *os02g10 = to_os02g10(sd);
868
869 __os02g10_power_off(os02g10);
870
871 return 0;
872 }
873
874 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
os02g10_open(struct v4l2_subdev * sd,struct v4l2_subdev_fh * fh)875 static int os02g10_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
876 {
877 struct os02g10 *os02g10 = to_os02g10(sd);
878 struct v4l2_mbus_framefmt *try_fmt =
879 v4l2_subdev_get_try_format(sd, fh->pad, 0);
880 const struct os02g10_mode *def_mode = &supported_modes[0];
881
882 mutex_lock(&os02g10->mutex);
883 /* Initialize try_fmt */
884 try_fmt->width = def_mode->width;
885 try_fmt->height = def_mode->height;
886 try_fmt->code = def_mode->bus_fmt;
887 try_fmt->field = V4L2_FIELD_NONE;
888
889 mutex_unlock(&os02g10->mutex);
890 /* No crop or compose */
891
892 return 0;
893 }
894 #endif
895
os02g10_enum_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_frame_interval_enum * fie)896 static int os02g10_enum_frame_interval(struct v4l2_subdev *sd,
897 struct v4l2_subdev_pad_config *cfg,
898 struct v4l2_subdev_frame_interval_enum *fie)
899 {
900 struct os02g10 *os02g10 = to_os02g10(sd);
901
902 if (fie->index >= os02g10->cfg_num)
903 return -EINVAL;
904
905 fie->code = supported_modes[fie->index].bus_fmt;
906 fie->width = supported_modes[fie->index].width;
907 fie->height = supported_modes[fie->index].height;
908 fie->interval = supported_modes[fie->index].max_fps;
909 fie->reserved[0] = supported_modes[fie->index].hdr_mode;
910 return 0;
911 }
912
913 static const struct dev_pm_ops os02g10_pm_ops = {
914 SET_RUNTIME_PM_OPS(os02g10_runtime_suspend,
915 os02g10_runtime_resume, NULL)
916 };
917
918 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
919 static const struct v4l2_subdev_internal_ops os02g10_internal_ops = {
920 .open = os02g10_open,
921 };
922 #endif
923
924 static const struct v4l2_subdev_core_ops os02g10_core_ops = {
925 .s_power = os02g10_s_power,
926 .ioctl = os02g10_ioctl,
927 #ifdef CONFIG_COMPAT
928 .compat_ioctl32 = os02g10_compat_ioctl32,
929 #endif
930 };
931
932 static const struct v4l2_subdev_video_ops os02g10_video_ops = {
933 .s_stream = os02g10_s_stream,
934 .g_frame_interval = os02g10_g_frame_interval,
935 };
936
937 static const struct v4l2_subdev_pad_ops os02g10_pad_ops = {
938 .enum_mbus_code = os02g10_enum_mbus_code,
939 .enum_frame_size = os02g10_enum_frame_sizes,
940 .enum_frame_interval = os02g10_enum_frame_interval,
941 .get_fmt = os02g10_get_fmt,
942 .set_fmt = os02g10_set_fmt,
943 .get_mbus_config = os02g10_g_mbus_config,
944 };
945
946 static const struct v4l2_subdev_ops os02g10_subdev_ops = {
947 .core = &os02g10_core_ops,
948 .video = &os02g10_video_ops,
949 .pad = &os02g10_pad_ops,
950 };
951
952
os02g10_get_gain_reg(u32 total_gain,u32 * again,u32 * dgain)953 static void os02g10_get_gain_reg(u32 total_gain, u32* again, u32* dgain)
954 {
955 u32 step = 0;
956 if (total_gain < 256) { /* 1x gain ~ 16x gain*/
957 *again = total_gain;
958 *dgain = 0x40;
959 } else if (total_gain < 512) { /* 16x gain ~ 32x gain */
960 step = (total_gain - 256) * 0x40 / 256;
961
962 *again = 0xff;
963 *dgain = 0x40 + step;
964 } else if (total_gain < 1024) { /* 32x gain ~ 64x gain */
965 step = (total_gain - 512) * 0x80 / 512;
966
967 *again = 0xff;
968 *dgain = 0x80 + step;
969 } else if (total_gain < 2048) { /* 64x gain ~ 128x gain */
970 step = (total_gain - 1024) * 0x100 / 1024;
971
972 *again = 0xff;
973 *dgain = 0x100 + step;
974 } else if (total_gain < 4096) { /* 128x gain ~ 256x gain */
975 step = (total_gain - 2048) * 0x200 / 2048;
976
977 *again = 0xff;
978 *dgain = 0x200 + step;
979 } else if (total_gain <= 8192) { /* 256x gain ~ 512x gain */
980 step = (total_gain - 4096) * 0x400 / 4096;
981
982 *again = 0xff;
983 *dgain = (0x400 + step) > 0x7ff ? 0x7ff : (0x400 + step);
984 }
985 }
986
os02g10_set_ctrl(struct v4l2_ctrl * ctrl)987 static int os02g10_set_ctrl(struct v4l2_ctrl *ctrl)
988 {
989 struct os02g10 *os02g10 = container_of(ctrl->handler,
990 struct os02g10, ctrl_handler);
991 struct i2c_client *client = os02g10->client;
992 s64 max;
993 int ret = 0;
994 u32 again = 0, dgain = 0;
995
996 /* Propagate change of current control to all related controls */
997 switch (ctrl->id) {
998 case V4L2_CID_VBLANK:
999 /* Update max exposure while meeting expected vblanking */
1000 max = os02g10->cur_mode->height + ctrl->val - 8;
1001 __v4l2_ctrl_modify_range(os02g10->exposure,
1002 os02g10->exposure->minimum, max,
1003 os02g10->exposure->step,
1004 os02g10->exposure->default_value);
1005 break;
1006 }
1007
1008 if (!pm_runtime_get_if_in_use(&client->dev))
1009 return 0;
1010
1011 switch (ctrl->id) {
1012 case V4L2_CID_EXPOSURE:
1013 ret = os02g10_write_reg(os02g10->client,
1014 OS02G10_REG_PAGE_SELECT, 0x1);
1015 ret |= os02g10_write_reg(os02g10->client,
1016 OS02G10_REG_EXP_H, (ctrl->val >> 8) & 0xFF);
1017 ret |= os02g10_write_reg(os02g10->client,
1018 OS02G10_REG_EXP_L, ctrl->val & 0xFF);
1019 ret |= os02g10_write_reg(os02g10->client,
1020 OS02G10_REG_RESTART, 0x01);
1021 dev_dbg(&client->dev, "set exposure 0x%x\n", ctrl->val);
1022 break;
1023 case V4L2_CID_ANALOGUE_GAIN:
1024 os02g10_get_gain_reg(ctrl->val, &again, &dgain);
1025
1026 ret = os02g10_write_reg(os02g10->client,
1027 OS02G10_REG_PAGE_SELECT, 0x01);
1028 ret |= os02g10_write_reg(os02g10->client,
1029 OS02G10_REG_AGAIN, again);
1030 ret |= os02g10_write_reg(os02g10->client,
1031 OS02G10_REG_DGAIN_H, dgain >> 8);
1032 ret |= os02g10_write_reg(os02g10->client,
1033 OS02G10_REG_DGAIN_L, (dgain & 0xff));
1034 ret |= os02g10_write_reg(os02g10->client,
1035 OS02G10_REG_RESTART, 0x01);
1036
1037 dev_dbg(&client->dev, "set gain 0x%x, again = %#x(%u), dgain = %#x(%u)\n",
1038 ctrl->val, again, again, dgain, dgain);
1039 break;
1040 case V4L2_CID_VBLANK:
1041 ret = os02g10_write_reg(os02g10->client,
1042 OS02G10_REG_PAGE_SELECT, 0x01);
1043 ret |= os02g10_write_reg(os02g10->client,
1044 OS02G10_REG_VBLANK_H, (ctrl->val >> 8) & 0xFF);
1045 ret |= os02g10_write_reg(os02g10->client,
1046 OS02G10_REG_VBLANK_L, ctrl->val & 0xFF);
1047 ret |= os02g10_write_reg(os02g10->client,
1048 OS02G10_REG_RESTART, 0x01);
1049 dev_dbg(&client->dev, "set vblank 0x%x\n", ctrl->val);
1050 break;
1051 case V4L2_CID_TEST_PATTERN:
1052 break;
1053 case V4L2_CID_HFLIP:
1054 if (ctrl->val)
1055 os02g10->flip |= MIRROR_BIT_MASK;
1056 else
1057 os02g10->flip &= ~MIRROR_BIT_MASK;
1058
1059 ret = os02g10_write_reg(os02g10->client,
1060 OS02G10_REG_PAGE_SELECT, 0x01);
1061 ret |= os02g10_write_reg(os02g10->client,
1062 OS02G10_FLIP_REG, os02g10->flip);
1063 ret |= os02g10_write_reg(os02g10->client,
1064 OS02G10_REG_PAGE_SELECT, 0x02);
1065 ret |= os02g10_write_reg(os02g10->client,
1066 OS02G10_REG_BAYER_ORDER, 0x32);
1067 ret |= os02g10_write_reg(os02g10->client,
1068 OS02G10_REG_PAGE_SELECT, 0x01);
1069 ret |= os02g10_write_reg(os02g10->client,
1070 OS02G10_REG_RESTART, 0x01);
1071 dev_dbg(&client->dev, "set hflip 0x%x\n", os02g10->flip);
1072 break;
1073 case V4L2_CID_VFLIP:
1074 if (ctrl->val)
1075 os02g10->flip |= FLIP_BIT_MASK;
1076 else
1077 os02g10->flip &= ~FLIP_BIT_MASK;
1078
1079 ret = os02g10_write_reg(os02g10->client,
1080 OS02G10_REG_PAGE_SELECT, 0x01);
1081 ret |= os02g10_write_reg(os02g10->client,
1082 OS02G10_FLIP_REG, os02g10->flip);
1083 ret |= os02g10_write_reg(os02g10->client,
1084 OS02G10_REG_PAGE_SELECT, 0x02);
1085 ret |= os02g10_write_reg(os02g10->client,
1086 OS02G10_REG_BAYER_ORDER, 0x32);
1087 ret |= os02g10_write_reg(os02g10->client,
1088 OS02G10_REG_PAGE_SELECT, 0x01);
1089 ret |= os02g10_write_reg(os02g10->client,
1090 OS02G10_REG_RESTART, 0x01);
1091 dev_dbg(&client->dev, "set vflip 0x%x\n", os02g10->flip);
1092 break;
1093 default:
1094 dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
1095 __func__, ctrl->id, ctrl->val);
1096 break;
1097 }
1098 pm_runtime_put(&client->dev);
1099
1100 return ret;
1101 }
1102
1103 static const struct v4l2_ctrl_ops os02g10_ctrl_ops = {
1104 .s_ctrl = os02g10_set_ctrl,
1105 };
1106
os02g10_initialize_controls(struct os02g10 * os02g10)1107 static int os02g10_initialize_controls(struct os02g10 *os02g10)
1108 {
1109 const struct os02g10_mode *mode;
1110 struct v4l2_ctrl_handler *handler;
1111 s64 exposure_max, vblank_def;
1112 u32 h_blank;
1113 int ret;
1114 u64 dst_link_freq = 0;
1115 u64 dst_pixel_rate = 0;
1116
1117 handler = &os02g10->ctrl_handler;
1118 mode = os02g10->cur_mode;
1119 ret = v4l2_ctrl_handler_init(handler, 9);
1120 if (ret)
1121 return ret;
1122 handler->lock = &os02g10->mutex;
1123
1124 os02g10->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
1125 V4L2_CID_LINK_FREQ,
1126 1, 0,
1127 link_freq_menu_items);
1128
1129 if (os02g10->cur_mode->bus_fmt == MEDIA_BUS_FMT_SBGGR10_1X10) {
1130 dst_link_freq = 0;
1131 dst_pixel_rate = PIXEL_RATE_WITH_360M;
1132 }
1133 /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
1134 os02g10->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
1135 V4L2_CID_PIXEL_RATE,
1136 0, PIXEL_RATE_WITH_360M,
1137 1, dst_pixel_rate);
1138
1139 __v4l2_ctrl_s_ctrl(os02g10->link_freq,
1140 dst_link_freq);
1141
1142 h_blank = mode->hts_def - mode->width;
1143 os02g10->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
1144 h_blank, h_blank, 1, h_blank);
1145 if (os02g10->hblank)
1146 os02g10->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1147
1148 vblank_def = mode->vts_def - mode->height;
1149 os02g10->vblank = v4l2_ctrl_new_std(handler, &os02g10_ctrl_ops,
1150 V4L2_CID_VBLANK, vblank_def,
1151 OS02G10_VTS_MAX - mode->height,
1152 1, vblank_def);
1153
1154 exposure_max = mode->vts_def - 8;
1155 os02g10->exposure = v4l2_ctrl_new_std(handler, &os02g10_ctrl_ops,
1156 V4L2_CID_EXPOSURE, OS02G10_EXPOSURE_MIN,
1157 exposure_max, OS02G10_EXPOSURE_STEP,
1158 mode->exp_def);
1159
1160 os02g10->anal_gain = v4l2_ctrl_new_std(handler, &os02g10_ctrl_ops,
1161 V4L2_CID_ANALOGUE_GAIN, OS02G10_GAIN_MIN,
1162 OS02G10_GAIN_MAX, OS02G10_GAIN_STEP,
1163 OS02G10_GAIN_DEFAULT);
1164
1165 v4l2_ctrl_new_std(handler, &os02g10_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
1166
1167 v4l2_ctrl_new_std(handler, &os02g10_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
1168
1169 os02g10->flip = 0;
1170
1171 if (handler->error) {
1172 ret = handler->error;
1173 dev_err(&os02g10->client->dev,
1174 "Failed to init controls(%d)\n", ret);
1175 goto err_free_handler;
1176 }
1177
1178 os02g10->subdev.ctrl_handler = handler;
1179 os02g10->has_init_exp = false;
1180
1181 return 0;
1182
1183 err_free_handler:
1184 v4l2_ctrl_handler_free(handler);
1185
1186 return ret;
1187 }
1188
os02g10_check_sensor_id(struct os02g10 * os02g10,struct i2c_client * client)1189 static int os02g10_check_sensor_id(struct os02g10 *os02g10,
1190 struct i2c_client *client)
1191 {
1192 struct device *dev = &os02g10->client->dev;
1193 u8 id_h = 0, id_l = 0;
1194 u32 id = 0;
1195 int ret;
1196
1197 ret = os02g10_read_reg(client, OS02G10_REG_CHIP_ID_H, &id_h);
1198 ret |= os02g10_read_reg(client, OS02G10_REG_CHIP_ID_L, &id_l);
1199
1200 id = SENSOR_ID(id_h, id_l);
1201 if (id != OS02G10_CHIP_ID) {
1202 dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
1203 return -ENODEV;
1204 }
1205 dev_info(dev, "Detected OV%06x sensor\n", OS02G10_CHIP_ID);
1206 return 0;
1207 }
1208
os02g10_configure_regulators(struct os02g10 * os02g10)1209 static int os02g10_configure_regulators(struct os02g10 *os02g10)
1210 {
1211 unsigned int i;
1212
1213 for (i = 0; i < OS02G10_NUM_SUPPLIES; i++)
1214 os02g10->supplies[i].supply = OS02G10_supply_names[i];
1215
1216 return devm_regulator_bulk_get(&os02g10->client->dev,
1217 OS02G10_NUM_SUPPLIES,
1218 os02g10->supplies);
1219 }
1220
os02g10_probe(struct i2c_client * client,const struct i2c_device_id * id)1221 static int os02g10_probe(struct i2c_client *client,
1222 const struct i2c_device_id *id)
1223 {
1224 struct device *dev = &client->dev;
1225 struct device_node *node = dev->of_node;
1226 struct os02g10 *os02g10;
1227 struct v4l2_subdev *sd;
1228 char facing[2];
1229 int ret;
1230 u32 i, hdr_mode = 0;
1231
1232 dev_info(dev, "driver version: %02x.%02x.%02x",
1233 DRIVER_VERSION >> 16,
1234 (DRIVER_VERSION & 0xff00) >> 8,
1235 DRIVER_VERSION & 0x00ff);
1236
1237 os02g10 = devm_kzalloc(dev, sizeof(*os02g10), GFP_KERNEL);
1238 if (!os02g10)
1239 return -ENOMEM;
1240
1241 ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
1242 &os02g10->module_index);
1243 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
1244 &os02g10->module_facing);
1245 ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
1246 &os02g10->module_name);
1247 ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
1248 &os02g10->len_name);
1249 if (ret) {
1250 dev_err(dev, "could not get module information!\n");
1251 return -EINVAL;
1252 }
1253
1254 ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE,
1255 &hdr_mode);
1256 if (ret) {
1257 hdr_mode = NO_HDR;
1258 dev_warn(dev, " Get hdr mode failed! no hdr default\n");
1259 }
1260 os02g10->cfg_num = ARRAY_SIZE(supported_modes);
1261 for (i = 0; i < os02g10->cfg_num; i++) {
1262 if (hdr_mode == supported_modes[i].hdr_mode) {
1263 os02g10->cur_mode = &supported_modes[i];
1264 break;
1265 }
1266 }
1267 os02g10->client = client;
1268
1269 os02g10->xvclk = devm_clk_get(dev, "xvclk");
1270 if (IS_ERR(os02g10->xvclk)) {
1271 dev_err(dev, "Failed to get xvclk\n");
1272 return -EINVAL;
1273 }
1274
1275 os02g10->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
1276 if (IS_ERR(os02g10->reset_gpio))
1277 dev_warn(dev, "Failed to get reset-gpios\n");
1278
1279 os02g10->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS);
1280 if (IS_ERR(os02g10->pwdn_gpio))
1281 dev_warn(dev, "Failed to get pwdn-gpios\n");
1282
1283 os02g10->pinctrl = devm_pinctrl_get(dev);
1284 if (!IS_ERR(os02g10->pinctrl)) {
1285 os02g10->pins_default =
1286 pinctrl_lookup_state(os02g10->pinctrl,
1287 OF_CAMERA_PINCTRL_STATE_DEFAULT);
1288 if (IS_ERR(os02g10->pins_default))
1289 dev_err(dev, "could not get default pinstate\n");
1290
1291 os02g10->pins_sleep =
1292 pinctrl_lookup_state(os02g10->pinctrl,
1293 OF_CAMERA_PINCTRL_STATE_SLEEP);
1294 if (IS_ERR(os02g10->pins_sleep))
1295 dev_err(dev, "could not get sleep pinstate\n");
1296 } else {
1297 dev_err(dev, "no pinctrl\n");
1298 }
1299
1300 ret = os02g10_configure_regulators(os02g10);
1301 if (ret) {
1302 dev_err(dev, "Failed to get power regulators\n");
1303 return ret;
1304 }
1305
1306 mutex_init(&os02g10->mutex);
1307
1308 sd = &os02g10->subdev;
1309 v4l2_i2c_subdev_init(sd, client, &os02g10_subdev_ops);
1310 ret = os02g10_initialize_controls(os02g10);
1311 if (ret)
1312 goto err_destroy_mutex;
1313
1314 ret = __os02g10_power_on(os02g10);
1315 if (ret)
1316 goto err_free_handler;
1317
1318 ret = os02g10_check_sensor_id(os02g10, client);
1319 if (ret)
1320 goto err_power_off;
1321
1322 #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
1323 sd->internal_ops = &os02g10_internal_ops;
1324 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1325 #endif
1326 #if defined(CONFIG_MEDIA_CONTROLLER)
1327 os02g10->pad.flags = MEDIA_PAD_FL_SOURCE;
1328 sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
1329 ret = media_entity_pads_init(&sd->entity, 1, &os02g10->pad);
1330 if (ret < 0)
1331 goto err_power_off;
1332 #endif
1333
1334 memset(facing, 0, sizeof(facing));
1335 if (strcmp(os02g10->module_facing, "back") == 0)
1336 facing[0] = 'b';
1337 else
1338 facing[0] = 'f';
1339
1340 snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
1341 os02g10->module_index, facing,
1342 OS02G10_NAME, dev_name(sd->dev));
1343 ret = v4l2_async_register_subdev_sensor_common(sd);
1344 if (ret) {
1345 dev_err(dev, "v4l2 async register subdev failed\n");
1346 goto err_clean_entity;
1347 }
1348
1349 pm_runtime_set_active(dev);
1350 pm_runtime_enable(dev);
1351 pm_runtime_idle(dev);
1352
1353 return 0;
1354
1355 err_clean_entity:
1356 #if defined(CONFIG_MEDIA_CONTROLLER)
1357 media_entity_cleanup(&sd->entity);
1358 #endif
1359 err_power_off:
1360 __os02g10_power_off(os02g10);
1361 err_free_handler:
1362 v4l2_ctrl_handler_free(&os02g10->ctrl_handler);
1363 err_destroy_mutex:
1364 mutex_destroy(&os02g10->mutex);
1365
1366 return ret;
1367 }
1368
os02g10_remove(struct i2c_client * client)1369 static int os02g10_remove(struct i2c_client *client)
1370 {
1371 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1372 struct os02g10 *os02g10 = to_os02g10(sd);
1373
1374 v4l2_async_unregister_subdev(sd);
1375 #if defined(CONFIG_MEDIA_CONTROLLER)
1376 media_entity_cleanup(&sd->entity);
1377 #endif
1378 v4l2_ctrl_handler_free(&os02g10->ctrl_handler);
1379 mutex_destroy(&os02g10->mutex);
1380
1381 pm_runtime_disable(&client->dev);
1382 if (!pm_runtime_status_suspended(&client->dev))
1383 __os02g10_power_off(os02g10);
1384 pm_runtime_set_suspended(&client->dev);
1385
1386 return 0;
1387 }
1388
1389 #if IS_ENABLED(CONFIG_OF)
1390 static const struct of_device_id os02g10_of_match[] = {
1391 { .compatible = "ovti,os02g10" },
1392 {},
1393 };
1394 MODULE_DEVICE_TABLE(of, os02g10_of_match);
1395 #endif
1396
1397 static const struct i2c_device_id os02g10_match_id[] = {
1398 { "ovti,os02g10", 0 },
1399 { },
1400 };
1401
1402 static struct i2c_driver os02g10_i2c_driver = {
1403 .driver = {
1404 .name = OS02G10_NAME,
1405 .pm = &os02g10_pm_ops,
1406 .of_match_table = of_match_ptr(os02g10_of_match),
1407 },
1408 .probe = &os02g10_probe,
1409 .remove = &os02g10_remove,
1410 .id_table = os02g10_match_id,
1411 };
1412
1413 #ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
1414 module_i2c_driver(os02g10_i2c_driver);
1415 #else
sensor_mod_init(void)1416 static int __init sensor_mod_init(void)
1417 {
1418 return i2c_add_driver(&os02g10_i2c_driver);
1419 }
1420
sensor_mod_exit(void)1421 static void __exit sensor_mod_exit(void)
1422 {
1423 i2c_del_driver(&os02g10_i2c_driver);
1424 }
1425
1426 device_initcall_sync(sensor_mod_init);
1427 module_exit(sensor_mod_exit);
1428 #endif
1429
1430 MODULE_DESCRIPTION("OmniVision os02g10 sensor driver");
1431 MODULE_LICENSE("GPL v2");
1432