Searched refs:NUM_GFXCLK_DPM_LEVELS (Results 1 – 10 of 10) sorted by relevance
37 #define NUM_GFXCLK_DPM_LEVELS 8 macro46 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)180 PllSetting_t GfxclkLevel [NUM_GFXCLK_DPM_LEVELS];229 uint8_t CksEnable[NUM_GFXCLK_DPM_LEVELS];230 uint8_t CksVidOffset[NUM_GFXCLK_DPM_LEVELS];294 …uint8_t StaticVoltageOffsetVid[NUM_GFXCLK_DPM_LEVELS]; /* This values are added on to the fin…315 uint8_t AcgEnable[NUM_GFXCLK_DPM_LEVELS];320 uint32_t AcgFreqTable[NUM_GFXCLK_DPM_LEVELS];354 float AvfsGbCksOn[NUM_GFXCLK_DPM_LEVELS];355 float AcBtcGbCksOn[NUM_GFXCLK_DPM_LEVELS];[all …]
36 #define NUM_GFXCLK_DPM_LEVELS 16 macro51 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)419 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ];
34 #define NUM_GFXCLK_DPM_LEVELS 16 macro44 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)514 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz
34 #define NUM_GFXCLK_DPM_LEVELS 16 macro53 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)655 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz
35 #define NUM_GFXCLK_DPM_LEVELS 16 macro50 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)584 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ]; // In MHz
35 #define NUM_GFXCLK_DPM_LEVELS 16 macro48 #define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)307 uint16_t FreqTableGfx [NUM_GFXCLK_DPM_LEVELS ];
313 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1737 while (i < NUM_GFXCLK_DPM_LEVELS) { in vega10_populate_all_graphic_levels()3150 NUM_GFXCLK_DPM_LEVELS), in vega10_get_pp_table_entry_callback_func()
1599 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) in arcturus_dump_pptable()
2046 for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++) in sienna_cichlid_dump_pptable()