Searched refs:MV_ETH_REGS_BASE (Results 1 – 2 of 2) sorted by relevance
148 #define MV_ETH_REGS_BASE(port) MV_ETH_REGS_OFFSET(port) macro151 #define SGMII_PWR_PLL_CTRL_REG(port) (MV_ETH_REGS_BASE(port) + 0xE04)152 #define SGMII_DIG_LP_ENA_REG(port) (MV_ETH_REGS_BASE(port) + 0xE8C)153 #define SGMII_REF_CLK_SEL_REG(port) (MV_ETH_REGS_BASE(port) + 0xF18)154 #define SGMII_SERDES_CFG_REG(port) (MV_ETH_REGS_BASE(port) + 0x4A0)155 #define SGMII_SERDES_STAT_REG(port) (MV_ETH_REGS_BASE(port) + 0x4A4)156 #define SGMII_COMPHY_CTRL_REG(port) (MV_ETH_REGS_BASE(port) + 0xF20)157 #define QSGMII_GEN_1_SETTING_REG(port) (MV_ETH_REGS_BASE(port) + 0xE38)158 #define QSGMII_SERDES_CFG_REG(port) (MV_ETH_REGS_BASE(port) + 0x4a0)
1145 reg_write(MV_ETH_REGS_BASE in serdes_phy_config()1149 DEBUG_WR_REG(MV_ETH_REGS_BASE in serdes_phy_config()1154 reg_write(MV_ETH_REGS_BASE in serdes_phy_config()1158 DEBUG_WR_REG(MV_ETH_REGS_BASE in serdes_phy_config()