Searched refs:MMU_REG_BASE (Results 1 – 2 of 2) sorted by relevance
68 MMU_REG_BASE ,
65 #define MMU_REG_BASE 0xcf000000 macro1225 #define ADR_MMU_CTRL (MMU_REG_BASE+0x00000000)1226 #define ADR_HS_CTRL (MMU_REG_BASE+0x00000004)1227 #define ADR_CPU_POR0_7 (MMU_REG_BASE+0x00000008)1228 #define ADR_CPU_POR8_F (MMU_REG_BASE+0x0000000c)1229 #define ADR_REG_LEN_CTRL (MMU_REG_BASE+0x00000010)1230 #define ADR_DMN_READ_BYPASS (MMU_REG_BASE+0x00000014)1231 #define ADR_ALC_RLS_ABORT (MMU_REG_BASE+0x00000018)1232 #define ADR_DEBUG_CTL (MMU_REG_BASE+0x00000020)1233 #define ADR_DEBUG_OUT (MMU_REG_BASE+0x00000024)[all …]