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Searched refs:MMU_REG (Results 1 – 17 of 17) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/arm/midgard/backend/gpu/
H A Dmali_kbase_mmu_hw_direct.c145 new_mask = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK), NULL); in kbase_mmu_interrupt()
147 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0, NULL); in kbase_mmu_interrupt()
245 tmp = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK), NULL); in kbase_mmu_interrupt()
247 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), new_mask, NULL); in kbase_mmu_interrupt()
373 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), pf_bf_mask, kctx); in kbase_mmu_hw_clear_fault()
396 irq_mask = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK), kctx) | in kbase_mmu_hw_enable_fault()
403 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), irq_mask, kctx); in kbase_mmu_hw_enable_fault()
H A Dmali_kbase_irq_linux.c94 val = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_STATUS), NULL); in kbase_mmu_irq_handler()
269 val = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_STATUS), NULL); in kbase_mmu_irq_test_handler()
281 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), val, NULL); in kbase_mmu_irq_test_handler()
315 rawstat_offset = MMU_REG(MMU_IRQ_RAWSTAT); in kbasep_common_test_interrupt()
316 mask_offset = MMU_REG(MMU_IRQ_MASK); in kbasep_common_test_interrupt()
H A Dmali_kbase_debug_job_fault_backend.c115 kctx->reg_dump[offset] = MMU_REG(mmu_reg_snapshot[i]); in kbase_debug_job_fault_reg_snapshot_init()
H A Dmali_kbase_pm_driver.c1022 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), 0xFFFFFFFF, NULL); in kbase_pm_enable_interrupts()
1023 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0xFFFFFFFF, NULL); in kbase_pm_enable_interrupts()
1044 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0, NULL); in kbase_pm_disable_interrupts_nolock()
1045 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), 0xFFFFFFFF, NULL); in kbase_pm_disable_interrupts_nolock()
H A Dmali_kbase_jm_hw.c1138 kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_RAWSTAT), NULL), in kbase_debug_dump_registers()
1143 kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK), NULL)); in kbase_debug_dump_registers()
/OK3568_Linux_fs/kernel/include/uapi/gpu/arm/bifrost/gpu/
H A Dmali_kbase_gpu_regmap.h74 #define MMU_REG(r) (MEMORY_MANAGEMENT_BASE + (r)) macro
85 #define MMU_AS_REG(n, r) (MMU_REG(MMU_AS0 + ((n) << 6)) + (r))
/OK3568_Linux_fs/kernel/drivers/gpu/arm/bifrost/backend/gpu/
H A Dmali_kbase_irq_linux.c102 val = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_STATUS)); in kbase_mmu_irq_handler()
301 val = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_STATUS)); in kbase_mmu_irq_test_handler()
313 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), val); in kbase_mmu_irq_test_handler()
347 rawstat_offset = MMU_REG(MMU_IRQ_RAWSTAT); in kbasep_common_test_interrupt()
348 mask_offset = MMU_REG(MMU_IRQ_MASK); in kbasep_common_test_interrupt()
H A Dmali_kbase_debug_job_fault_backend.c121 kctx->reg_dump[offset] = MMU_REG(mmu_reg_snapshot[i]); in kbase_debug_job_fault_reg_snapshot_init()
H A Dmali_kbase_model_linux.c99 MMU_REG(MMU_IRQ_STATUS)))) { in serve_mmu_irq()
H A Dmali_kbase_model_dummy.c1412 else if (addr == MMU_REG(MMU_IRQ_MASK)) {
1414 } else if (addr == MMU_REG(MMU_IRQ_CLEAR)) {
1976 } else if (addr == MMU_REG(MMU_IRQ_MASK)) {
1978 } else if (addr == MMU_REG(MMU_IRQ_RAWSTAT)) {
1980 } else if (addr == MMU_REG(MMU_IRQ_STATUS)) {
H A Dmali_kbase_pm_driver.c2537 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), 0xFFFFFFFF);
2540 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0xFFFF);
2542 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0xFFFFFFFF);
2562 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0);
2563 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), 0xFFFFFFFF);
H A Dmali_kbase_jm_hw.c1055 kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_RAWSTAT)), in kbase_debug_dump_registers()
1060 kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK))); in kbase_debug_dump_registers()
/OK3568_Linux_fs/kernel/drivers/gpu/arm/bifrost/mmu/backend/
H A Dmali_kbase_mmu_jm.c325 new_mask = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK)); in kbase_mmu_interrupt()
327 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0); in kbase_mmu_interrupt()
409 tmp = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK)); in kbase_mmu_interrupt()
411 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), new_mask); in kbase_mmu_interrupt()
H A Dmali_kbase_mmu_csf.c371 new_mask = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK)); in kbase_mmu_interrupt()
373 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), 0); in kbase_mmu_interrupt()
435 tmp = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK)); in kbase_mmu_interrupt()
437 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), new_mask); in kbase_mmu_interrupt()
/OK3568_Linux_fs/kernel/drivers/gpu/arm/bifrost/mmu/
H A Dmali_kbase_mmu_hw_direct.c663 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_CLEAR), pf_bf_mask); in kbase_mmu_hw_clear_fault()
687 irq_mask = kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK)) | in kbase_mmu_hw_enable_fault()
695 kbase_reg_write(kbdev, MMU_REG(MMU_IRQ_MASK), irq_mask); in kbase_mmu_hw_enable_fault()
/OK3568_Linux_fs/kernel/drivers/gpu/arm/midgard/
H A Dmali_midg_regmap.h256 #define MMU_REG(r) (MEMORY_MANAGEMENT_BASE + (r)) macro
280 #define MMU_AS_REG(n, r) (MMU_REG(MMU_AS0 + ((n) << 6)) + (r))
/OK3568_Linux_fs/kernel/drivers/gpu/arm/bifrost/csf/
H A Dmali_kbase_csf_reset_gpu.c245 kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_RAWSTAT)), in kbase_csf_debug_dump_registers()
250 kbase_reg_read(kbdev, MMU_REG(MMU_IRQ_MASK))); in kbase_csf_debug_dump_registers()