Searched refs:MLX5E_NUM_INDIR_TIRS (Results 1 – 8 of 8) sorted by relevance
84 MLX5E_NUM_INDIR_TIRS = MLX5E_TT_ANY, enumerator259 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];
726 u32 rx_hash_fields[MLX5E_NUM_INDIR_TIRS];785 struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];786 struct mlx5e_tir inner_indir_tir[MLX5E_NUM_INDIR_TIRS];
812 return MLX5E_NUM_INDIR_TIRS; in flow_type_to_traffic_type()825 if (tt == MLX5E_NUM_INDIR_TIRS) in mlx5e_set_rss_hash_opt()876 if (tt == MLX5E_NUM_INDIR_TIRS) in mlx5e_get_rss_hash_opt()
2667 static const struct mlx5e_tirc_config tirc_default_config[MLX5E_NUM_INDIR_TIRS] = {2774 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { in mlx5e_modify_tirs_hash()2786 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { in mlx5e_modify_tirs_hash()2816 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { in mlx5e_modify_tirs_lro()3447 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { in mlx5e_create_indirect_tirs()3462 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) { in mlx5e_create_indirect_tirs()3532 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) in mlx5e_destroy_indirect_tirs()3539 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) in mlx5e_destroy_indirect_tirs()4860 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) in mlx5e_build_rss_params()
1590 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) in mlx5e_create_flow_steering()1601 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) in mlx5e_create_flow_steering()
807 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) in mlx5e_create_rep_ttc_table()
333 u32 indir_tirn[MLX5E_NUM_INDIR_TIRS];600 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) { in mlx5e_hairpin_create_indirect_tirs()630 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) in mlx5e_hairpin_destroy_indirect_tirs()644 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) in mlx5e_hairpin_set_ttc_params()
341 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) in mlx5i_create_flow_steering()