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Searched refs:MI_LOAD_REGISTER_IMM (Results 1 – 15 of 15) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/gt/
H A Dintel_ring_submission.c633 *cs++ = MI_LOAD_REGISTER_IMM(1); in load_pd_dir()
637 *cs++ = MI_LOAD_REGISTER_IMM(1); in load_pd_dir()
647 *cs++ = MI_LOAD_REGISTER_IMM(1); in load_pd_dir()
691 *cs++ = MI_LOAD_REGISTER_IMM(num_engines); in mi_set_context()
745 *cs++ = MI_LOAD_REGISTER_IMM(num_engines); in mi_set_context()
790 *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4); in remap_l3_slice()
H A Dintel_gpu_commands.h139 #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*(x)-1) macro
H A Dselftest_workarounds.c545 *cs++ = MI_LOAD_REGISTER_IMM(1); in check_dirty_whitelist()
558 *cs++ = MI_LOAD_REGISTER_IMM(1); in check_dirty_whitelist()
858 *cs++ = MI_LOAD_REGISTER_IMM(whitelist_writable_count(engine)); in scrub_whitelisted_registers()
H A Dgen7_renderclear.c398 batch_add(&cmds, MI_LOAD_REGISTER_IMM(2)); in emit_batch()
H A Dselftest_rps.c97 *cs++ = MI_LOAD_REGISTER_IMM(__NGPR__ * 2); in create_spin_counter()
105 *cs++ = MI_LOAD_REGISTER_IMM(1); in create_spin_counter()
H A Dintel_lrc.c623 *regs = MI_LOAD_REGISTER_IMM(count); in set_offsets()
3636 *cs++ = MI_LOAD_REGISTER_IMM(2 * GEN8_3LVL_PDPES) | MI_LRI_FORCE_POSTED; in emit_pdps()
3715 *batch++ = MI_LOAD_REGISTER_IMM(1); in gen8_emit_flush_coherentl3_wa()
3790 *batch++ = MI_LOAD_REGISTER_IMM(count); in emit_lri()
4717 *cs++ = MI_LOAD_REGISTER_IMM(1); in gen12_emit_aux_table_inv()
4840 *cs++ = MI_LOAD_REGISTER_IMM(hweight8(aux_inv)); in gen12_emit_flush()
H A Dselftest_lrc.c3035 *cs++ = MI_LOAD_REGISTER_IMM(1); in create_gpr_user()
4217 *cs++ = MI_LOAD_REGISTER_IMM(1); in preserved_virtual_engine()
5142 *cs++ = MI_LOAD_REGISTER_IMM(NUM_GPR_DW); in gpr_make_dirty()
5751 *cs++ = MI_LOAD_REGISTER_IMM(len); in load_context()
H A Dintel_workarounds.c747 *cs++ = MI_LOAD_REGISTER_IMM(wal->count); in intel_engine_emit_ctx_wa()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/gvt/
H A Dmmio_context.c216 *cs++ = MI_LOAD_REGISTER_IMM(count); in restore_context_mmio_for_inhibit()
249 *cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE); in restore_render_mocs_control_for_inhibit()
276 *cs++ = MI_LOAD_REGISTER_IMM(GEN9_MOCS_SIZE / 2); in restore_render_mocs_l3cc_for_inhibit()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/
H A Di915_cmd_parser.c219 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
476 CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W,
1275 if (cmd_desc_is(desc, MI_LOAD_REGISTER_IMM(1)) && in check_cmd()
H A Di915_perf.c1688 *cs++ = MI_LOAD_REGISTER_IMM(1); in alloc_noa_wait()
1706 *cs++ = MI_LOAD_REGISTER_IMM(1); in alloc_noa_wait()
1748 *cs++ = MI_LOAD_REGISTER_IMM(2); in alloc_noa_wait()
1817 *cs++ = MI_LOAD_REGISTER_IMM(n_lri); in write_cs_mi_lri()
2152 *cs++ = MI_LOAD_REGISTER_IMM(count); in gen8_load_flex()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/selftests/
H A Di915_perf.c336 *cs++ = MI_LOAD_REGISTER_IMM(32); in live_noa_gpr()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/gem/selftests/
H A Di915_gem_client_blt.c166 *cs++ = MI_LOAD_REGISTER_IMM(1); in prepare_blit()
/OK3568_Linux_fs/kernel/drivers/gpu/drm/i915/gem/
H A Di915_gem_context.c1256 *cs++ = MI_LOAD_REGISTER_IMM(2); in emit_ppgtt_update()
1278 *cs++ = MI_LOAD_REGISTER_IMM(2 * GEN8_3LVL_PDPES) | MI_LRI_FORCE_POSTED; in emit_ppgtt_update()
H A Di915_gem_execbuffer.c2242 *cs++ = MI_LOAD_REGISTER_IMM(4); in i915_reset_gen7_sol_offsets()