Searched refs:J721E_CLK_PARENT_44100 (Results 1 – 1 of 1) sorted by relevance
30 #define J721E_CLK_PARENT_44100 1 macro180 else if (!(rate % 11025) && priv->pll_rates[J721E_CLK_PARENT_44100]) in j721e_configure_refclk()181 clk_id = J721E_CLK_PARENT_44100; in j721e_configure_refclk()501 clocks->parent[J721E_CLK_PARENT_44100] = parent; in j721e_get_clocks()506 if (!clocks->parent[J721E_CLK_PARENT_44100] && in j721e_get_clocks()520 [J721E_CLK_PARENT_44100] = 1083801600, /* PLL15 */529 [J721E_CLK_PARENT_44100] = 1083801600, /* PLL15 */566 pll = clk_get_parent(domain_clocks->parent[J721E_CLK_PARENT_44100]); in j721e_calculate_rate_range()568 priv->pll_rates[J721E_CLK_PARENT_44100] = in j721e_calculate_rate_range()569 match_data->pll_rates[J721E_CLK_PARENT_44100]; in j721e_calculate_rate_range()[all …]