Searched refs:EXYNOS5_DREXI_TIMINGPOWER0 (Results 1 – 1 of 1) sorted by relevance
32 #define EXYNOS5_DREXI_TIMINGPOWER0 (0x003C) macro443 dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER0); in exynos5_dram_change_timings()445 dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER0); in exynos5_dram_change_timings()