Searched refs:DR0 (Results 1 – 7 of 7) sorted by relevance
318 data = readl(card->membase + DR0); in ns_read_sram()451 data = readl(card->membase + DR0); in ns_init_card()457 writel(0x00000008, card->membase + DR0); in ns_init_card()463 writel(0x00000022, card->membase + DR0); in ns_init_card()473 writel(0x00000002, card->membase + DR0); in ns_init_card()1036 writel(id1, card->membase + DR0); in push_rxbufs()2446 phy_regs[i] = readl(card->membase + DR0) & 0x000000FF; in ns_proc_read()2728 writel((u32) value, card->membase + DR0); in ns_phy_put()2746 data = readl(card->membase + DR0) & 0x000000FF; in ns_phy_get()
428 DR0 = 0x00, /* Data Register 0 R/W */ enumerator
31 DR0 - 0000000000000000, DR1 - 0000000000000000, DR2 - 0000000000000000
505 GPIO_FN(DR0),
44160 DR0-DR7 DMA setup channels:
107070100A8AEB0000041ED0000000000000000000000116841B48100000000000000FD0000000200000000000000000000000200000000.07070100A8B07C000081A40000000000000000000000016841263500000000000000FD0000000200000000000000000000000900000000.gitkeep07070100A8B07D000081A40000000000000000000000016841263500000000000000FD0000000200000000000000000000000B00000000.skip_fsck07070100A8AEB10000A1FF0000000000000000000000016841B0B600000007000000FD0000000200000000000000000000000400000000binusr/bin07070100A8B07E000081A400000000000000000000000168412635000001CC000000FD0000000200000000000000000000001100000000busybox. ...