| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/ |
| H A D | navi10_reg_init.c | 42 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); in navi10_reg_base_init()
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| H A D | navi12_reg_init.c | 42 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); in navi12_reg_base_init()
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| H A D | navi14_reg_init.c | 42 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); in navi14_reg_base_init()
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| H A D | sienna_cichlid_reg_init.c | 43 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); in sienna_cichlid_reg_base_init()
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| H A D | arct_reg_init.c | 42 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); in arct_reg_base_init()
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| H A D | vega10_reg_init.c | 44 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); in vega10_reg_base_init()
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| H A D | vega20_reg_init.c | 43 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i])); in vega20_reg_base_init()
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| /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/ |
| H A D | navi10_ip_offset.h | 49 static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0, 0, 0, 0, 0 } }, variable
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| H A D | navi12_ip_offset.h | 53 static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0, 0 } }, variable
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| H A D | navi14_ip_offset.h | 53 static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0, 0 } }, variable
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| H A D | vega20_ip_offset.h | 57 static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0, 0, 0, 0, 0 } }, variable
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| H A D | sienna_cichlid_ip_offset.h | 53 static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0, 0, 0 } }, variable
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| H A D | vega10_ip_offset.h | 73 static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0, 0, 0, 0 } }, variable
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| H A D | renoir_ip_offset.h | 67 static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x0240B800, 0, 0, 0 } }, variable
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| H A D | arct_ip_offset.h | 55 static const struct IP_BASE DF_BASE ={ { { { 0x00007000, 0x000125C0, 0x0040B800, 0, 0, 0… variable
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