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Searched refs:DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT (Results 1 – 10 of 10) sorted by relevance

/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_sh_mask.h5228 #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x00000000 macro
H A Ddce_8_0_sh_mask.h2888 #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0 macro
H A Ddce_10_0_sh_mask.h2686 #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0 macro
H A Ddce_11_0_sh_mask.h2700 #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0 macro
H A Ddce_11_2_sh_mask.h2940 #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT 0x0 macro
H A Ddce_12_0_sh_mask.h9001 #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT … macro
/OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_sh_mask.h39747 #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT … macro
H A Ddcn_2_1_0_sh_mask.h43053 #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT … macro
H A Ddcn_2_0_0_sh_mask.h48532 #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT … macro
H A Ddcn_3_0_0_sh_mask.h48904 #define DC_REF_CLK_CNTL__HSYNCA_OUTPUT_SEL__SHIFT … macro