Searched refs:CMU_REG9_PLL_POST_DIVBY2_SET (Results 1 – 1 of 1) sorted by relevance
186 #define CMU_REG9_PLL_POST_DIVBY2_SET(dst, src) \ macro862 val = CMU_REG9_PLL_POST_DIVBY2_SET(val, 0x1); in xgene_phy_sata_cfg_cmu_core()