Searched refs:CLK_PLL1_DIV1 (Results 1 – 2 of 2) sorted by relevance
84 #define CLK_PLL1_DIV1 0x20 macro
344 #define CLK_PLL1_DIV1 0x20 macro795 hsclk_sel |= CLK_PLL1_DIV1; in tcphy_cfg_dp_pll()