Searched refs:CLK_DIV_DISP1_0_VAL (Results 1 – 2 of 2) sorted by relevance
695 #define CLK_DIV_DISP1_0_VAL NOT_AVAILABLE macro880 #define CLK_DIV_DISP1_0_VAL 0x01050211 macro
936 writel(CLK_DIV_DISP1_0_VAL, &clk->div_disp10); in exynos5420_system_clock_init()