Searched refs:CLK_DIV_CPERI1_VAL (Results 1 – 2 of 2) sorted by relevance
700 #define CLK_DIV_CPERI1_VAL NOT_AVAILABLE macro885 #define CLK_DIV_CPERI1_VAL 0x3f3f0000 macro
961 writel(CLK_DIV_CPERI1_VAL, &clk->div_cperi1); in exynos5420_system_clock_init()