Searched refs:CLK_DIV_CDREX0_VAL (Results 1 – 2 of 2) sorted by relevance
507 #define CLK_DIV_CDREX0_VAL NOT_AVAILABLE macro775 #define CLK_DIV_CDREX0_VAL 0x30010100 macro
914 writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0); in exynos5420_system_clock_init()