Searched refs:BASE_MAX_NR_CLOCKS_REGULATORS (Results 1 – 8 of 8) sorted by relevance
114 WARN_ON(index >= BASE_MAX_NR_CLOCKS_REGULATORS)) in gpu_clk_data_init()176 for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) { in kbase_clk_rate_trace_manager_init()221 for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) { in kbase_clk_rate_trace_manager_term()246 for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) { in kbase_clk_rate_trace_manager_gpu_active()274 for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) { in kbase_clk_rate_trace_manager_gpu_idle()
468 real_freqs[BASE_MAX_NR_CLOCKS_REGULATORS]; in kbase_devfreq_init_core_mask_table()471 u32 opp_volts[BASE_MAX_NR_CLOCKS_REGULATORS]; in kbase_devfreq_init_core_mask_table()486 #if BASE_MAX_NR_CLOCKS_REGULATORS > 1 in kbase_devfreq_init_core_mask_table()
158 #define BASE_MAX_NR_CLOCKS_REGULATORS (4) macro407 struct kbase_clk_data *clks[BASE_MAX_NR_CLOCKS_REGULATORS];581 u64 real_freqs[BASE_MAX_NR_CLOCKS_REGULATORS];582 u32 opp_volts[BASE_MAX_NR_CLOCKS_REGULATORS];1070 struct clk *clocks[BASE_MAX_NR_CLOCKS_REGULATORS];1073 struct regulator *regulators[BASE_MAX_NR_CLOCKS_REGULATORS];1182 unsigned long current_freqs[BASE_MAX_NR_CLOCKS_REGULATORS];1183 unsigned long current_voltages[BASE_MAX_NR_CLOCKS_REGULATORS];
4566 for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) { in power_control_init()4646 for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) { in power_control_init()4659 for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) in power_control_init()4685 for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) { in power_control_term()4695 for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) { in power_control_term()
35 #ifndef BASE_MAX_NR_CLOCKS_REGULATORS36 #define BASE_MAX_NR_CLOCKS_REGULATORS 4 macro260 u64 cycle_count_elapsed[BASE_MAX_NR_CLOCKS_REGULATORS];261 u64 prev_cycle_count[BASE_MAX_NR_CLOCKS_REGULATORS];289 u64 cycle_counts[BASE_MAX_NR_CLOCKS_REGULATORS]; in kbasep_hwcnt_backend_csf_cc_initial_sample()310 u64 cycle_counts[BASE_MAX_NR_CLOCKS_REGULATORS]; in kbasep_hwcnt_backend_csf_cc_update()1828 if (csf_info->prfcnt_info.clk_cnt > BASE_MAX_NR_CLOCKS_REGULATORS) in kbase_hwcnt_backend_csf_metadata_init()
119 u64 cycle_count_elapsed[BASE_MAX_NR_CLOCKS_REGULATORS];120 u64 prev_cycle_count[BASE_MAX_NR_CLOCKS_REGULATORS];161 for (clk = 0; clk < BASE_MAX_NR_CLOCKS_REGULATORS; clk++) { in kbasep_hwcnt_backend_jm_gpu_info_init()
729 for (clk = 0; clk < BASE_MAX_NR_CLOCKS_REGULATORS; clk++) { in kbasep_hwcnt_backend_csf_if_fw_ctx_create()
96 struct clk_trace_snapshot snapshot[BASE_MAX_NR_CLOCKS_REGULATORS];839 for (i = 0; i < BASE_MAX_NR_CLOCKS_REGULATORS; i++) { in mali_kutf_clk_rate_trace_create_fixture()