1 /*
2 * Copyright (c) 2026, Qualcomm Technologies, Inc. and/or its subsidiaries.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 #include <lib/mmio.h>
8 #include <lib/utils_def.h>
9 #include <xpu_target_info.h>
10
11 struct xpu_err_pos_to_hal_map xpu_err_pos_to_hal_map
12 [ACC_XPU_ERR_INT_REG_NUM][ACC_XPU_ERR_NUM_PER_REG] = {
13 {
14 { BIT(1), XPU_TYPE_AOSS_CNOC_MPU },
15 { BIT(9), XPU_TYPE_SEC_CTRL_APU },
16 { BIT(10), XPU_TYPE_WPSS_MPU },
17 { BIT(16), XPU_TYPE_AOSS_MPU },
18 { BIT(18), XPU_TYPE_CNOC_GEMNOC_MPU },
19 { BIT(25), XPU_TYPE_LLCC_BROADCAST_MPU },
20 { BIT(26), XPU_TYPE_BIMC_MPU0 },
21 { BIT(27), XPU_TYPE_BIMC_MPU1 },
22 { BIT(30), XPU_TYPE_BOOT_ROM },
23 { BIT(31), XPU_TYPE_DC_NOC_NON_BROADCAST_MPU },
24 { 0, 0 },
25 },
26 {
27 { BIT(0), XPU_TYPE_IMEM_MPU },
28 { BIT(1), XPU_TYPE_ANOC1_MPU },
29 { BIT(2), XPU_TYPE_ANOC2_MPU },
30 { BIT(3), XPU_TYPE_MSS_MPU },
31 { BIT(6), XPU_TYPE_CNOC2_SS_MPU },
32 { BIT(10), XPU_TYPE_MSS_Q6_MPU },
33 { BIT(11), XPU_TYPE_IPA_0_GSI_TOP },
34 { BIT(13), XPU_TYPE_DC_NOC_SHRM_MPU },
35 { BIT(14), XPU_TYPE_PKA_APU },
36 { BIT(16), XPU_TYPE_IPC_MPU },
37 { BIT(30), XPU_TYPE_MSS_NAV_MPU },
38 { 0, 0 },
39 },
40 };
41
42 const struct xpu_intr_reg_dtls
43 xpu_non_sec_intr_status_reg[ACC_XPU_ERR_INT_REG_NUM] = {
44 {
45 HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_ADDR,
46 HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_0_RMSK,
47 },
48 {
49 HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_ADDR,
50 HWIO_TCSR_XPU3_NON_SEC_IRQ_STATUS_REG_1_RMSK,
51 },
52 };
53
54 const struct xpu_intr_reg_dtls
55 xpu_sec_intr_status_reg[ACC_XPU_ERR_INT_REG_NUM] = {
56 {
57 HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_ADDR,
58 HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_0_RMSK,
59 },
60 {
61 HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_ADDR,
62 HWIO_TCSR_XPU3_SEC_IRQ_STATUS_REG_1_RMSK,
63 },
64 };
65
66 const struct xpu_intr_reg_dtls
67 xpu_non_sec_intr_en_reg[ACC_XPU_ERR_INT_REG_NUM] = {
68 {
69 HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_ADDR,
70 HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_0_RMSK,
71 },
72 {
73 HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_ADDR,
74 HWIO_TCSR_XPU3_NON_SEC_IRQ_ENABLE_0_REG_1_RMSK,
75 },
76 };
77
78 const struct xpu_intr_reg_dtls xpu_sec_intr_en_reg[ACC_XPU_ERR_INT_REG_NUM] = {
79 {
80 HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_ADDR,
81 HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_0_RMSK,
82 },
83 {
84 HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_ADDR,
85 HWIO_TCSR_XPU3_SEC_IRQ_ENABLE_0_REG_1_RMSK,
86 },
87 };
88
89 struct xpu_base_addr_info g_xpu_base_addr_array[] = {
90 {
91 XPU_TYPE_DC_NOC_SHRM_MPU,
92 XPU_ADDR_TYPE(QHM_SHRM_MPU_XPU3_GCR0),
93 "DC_NOC_SHRM_MPU",
94 },
95 {
96 XPU_TYPE_PKA_APU,
97 XPU_ADDR_TYPE(PKA_WRAPPER_XPU3_GCR0),
98 "PKA_APU",
99 },
100 {
101 XPU_TYPE_IPC_MPU,
102 XPU_ADDR_TYPE(IPC_XPU3_GCR0),
103 "IPC_MPU",
104 },
105 {
106 XPU_TYPE_DC_NOC_NON_BROADCAST_MPU,
107 XPU_ADDR_TYPE(QHS_NON_BROADCAST_MPU_XPU3_GCR0),
108 "DC_NOC_NON_BROADCAST_MPU",
109 },
110 {
111 XPU_TYPE_IMEM_MPU,
112 XPU_ADDR_TYPE(OCIMEM_MPU_XPU3_GCR0),
113 "IMEM_MPU",
114 },
115 {
116 XPU_TYPE_BOOT_ROM,
117 XPU_ADDR_TYPE(BOOT_ROM_XPU3_GCR0),
118 "BOOT_ROM",
119 },
120 {
121 XPU_TYPE_IPA_0_GSI_TOP,
122 XPU_ADDR_TYPE(IPA_0_GSI_TOP_XPU3_GCR0),
123 "IPA_0_GSI_TOP",
124 },
125 {
126 XPU_TYPE_BIMC_MPU0,
127 XPU_ADDR_TYPE(LLCC0_LLCC_XPU3_GCR0),
128 "BIMC_MPU0",
129 },
130 {
131 XPU_TYPE_BIMC_MPU1,
132 XPU_ADDR_TYPE(LLCC1_LLCC_XPU3_GCR0),
133 "BIMC_MPU0",
134 },
135 {
136 XPU_TYPE_LLCC_BROADCAST_MPU,
137 XPU_ADDR_TYPE(LLCC_BROADCAST_LLCC_XPU3_GCR0),
138 "LLCC_BROADCAST_MPU",
139 },
140 {
141 XPU_TYPE_MSS_NAV_MPU,
142 XPU_ADDR_TYPE(SNOC_NAV_MS_MPU_XPU3_GCR0),
143 "MSS_NAV_MPU",
144 },
145 {
146 XPU_TYPE_MSS_MPU,
147 XPU_ADDR_TYPE(MODEM_MS_MPU_XPU3_GCR0),
148 "MSS_MPU",
149 },
150 {
151 XPU_TYPE_ANOC1_MPU,
152 XPU_ADDR_TYPE(SNOC_AGGRE1_MS_MPU_XPU3_GCR0),
153 "ANOC1_MPU",
154 },
155 {
156 XPU_TYPE_ANOC2_MPU,
157 XPU_ADDR_TYPE(SNOC_AGGRE2_MS_MPU_XPU3_GCR0),
158 "ANOC2_MPU",
159 },
160 {
161 XPU_TYPE_MSS_Q6_MPU,
162 XPU_ADDR_TYPE(MDSP_MS_MPU_XPU3_GCR0),
163 "MSS_Q6_MPU",
164 },
165 {
166 XPU_TYPE_AOSS_MPU,
167 XPU_ADDR_TYPE(AOSS_MPU_XPU3_GCR0),
168 "AOSS_MPU",
169 },
170 {
171 XPU_TYPE_SEC_CTRL_APU,
172 XPU_ADDR_TYPE(SEC_CTRL_APU_XPU3_GCR0),
173 "SEC_CTRL_APU",
174 },
175 {
176 XPU_TYPE_CNOC_GEMNOC_MPU,
177 XPU_ADDR_TYPE(CNOC_GEMNOC_MPU_XPU3_GCR0),
178 "CNOC_GEMNOC_MPU",
179 },
180 {
181 XPU_TYPE_CNOC2_SS_MPU,
182 XPU_ADDR_TYPE(CNOC2_SS_MPU_XPU3_GCR0),
183 "CNOC2_SS_MPU",
184 },
185 {
186 XPU_TYPE_WPSS_MPU,
187 XPU_ADDR_TYPE(WPSS_MPU_XPU3_GCR0),
188 "WPSS_MPU",
189 },
190 {
191 XPU_TYPE_AOSS_CNOC_MPU,
192 XPU_ADDR_TYPE(AOSS_CNOC_MPU_XPU3_GCR0),
193 "AOSS_CNOC_MPU",
194 },
195 };
196
197 uint32_t g_xpu_base_addr_array_count = ARRAY_SIZE(g_xpu_base_addr_array);
198
xpu_configure_tz(void)199 void xpu_configure_tz(void)
200 {
201 mmio_write_32(HWIO_IPA_0_GSI_TOP_XPU3_GCR0_ADDR + 0x8, 0x10f);
202 }
203