xref: /rk3399_ARM-atf/drivers/qti/accesscontrol/xpu/kodiak/xpu_static_config.c (revision 5de3e03dbd7c2da6748e294f423c83f9582f459c)
1 /*
2  * Copyright (c) 2026, Qualcomm Technologies, Inc. and/or its subsidiaries.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #include <lib/utils_def.h>
8 #include <xpu3.h>
9 #include <xpu_target_info.h>
10 
11 #include <platform_def.h>
12 
13 #define ANOC2_STATIC_REGION 3
14 #define MSS_Q6_STATIC_REGION 17
15 
16 struct rg_domain_ownership ramblur_pimem_mpu_rgs[] = {
17 	{ 7, APPS_S_DOMAIN },
18 };
19 
20 struct rg_partition_range ramblur_pimem_mpu_rg_addr[] = {
21 	{ 7, 0x0, 0x0 }, /* full p_imem range */
22 };
23 
24 struct rg_domain_ownership mss_q6_mpu_rgs[MSS_Q6_STATIC_REGION + 1 +
25 					  NUM_MODEM_MPU_PARTITIONS] = {
26 	{ 0, MSA_DOMAIN },  { 1, MSA_DOMAIN },	{ 2, MSA_DOMAIN },
27 	{ 3, MSA_DOMAIN },  { 4, MSA_DOMAIN },	{ 5, MSA_DOMAIN },
28 	{ 6, MSA_DOMAIN },  { 7, MSA_DOMAIN },	{ 8, MSA_DOMAIN },
29 	{ 9, MSA_DOMAIN },  { 10, MSA_DOMAIN }, { 11, MSA_DOMAIN },
30 	{ 12, MSA_DOMAIN }, { 13, MSA_DOMAIN }, { 14, MSA_DOMAIN },
31 	{ 15, MSA_DOMAIN }, { 16, MSA_DOMAIN }, { XPU_UMR_RG, APPS_NS_DOMAIN },
32 };
33 
34 struct rg_partition_range
35 	mss_q6_mpu_rg_addr[MSS_Q6_STATIC_REGION + NUM_MODEM_MPU_PARTITIONS] = {
36 		{ 0, 0x00008000, 0x007c0000 },	{ 1, 0x007e0000, 0x00940000 },
37 		{ 2, 0x00984000, 0x01c00000 },	{ 3, 0x01dc0000, 0x02000000 },
38 		{ 4, 0x04000000, 0x06002000 },	{ 5, 0x06003000, 0x08400000 },
39 		{ 6, 0x09000000, 0x09800000 },	{ 7, 0x0b000000, 0x0f00a000 },
40 		{ 8, 0x0f16d000, 0x0f177000 },	{ 9, 0x0f178000, 0x0f181000 },
41 		{ 10, 0x0f185000, 0x0f18b000 }, { 11, 0x16000000, 0x17000000 },
42 		{ 12, 0x146a8000, 0x146ab000 }, { 13, 0x80900000, 0x80b00000 },
43 		{ 14, 0x80860000, 0x80880000 }, { 15, 0x146a5000, 0x146a6000 },
44 		{ 16, 0xffffffff, 0xffffffff },
45 	};
46 
47 struct rg_domain_ownership
48 	anoc2_mpu_rgs[ANOC2_STATIC_REGION + 1 + NUM_MODEM_MPU_PARTITIONS] = {
49 		{ 0, MSA_DOMAIN },
50 		{ 6, MSA_DOMAIN },
51 		{ 7, MSA_DOMAIN },
52 		{ XPU_UMR_RG, APPS_NS_DOMAIN },
53 	};
54 
55 struct rg_partition_range
56 	anoc2_mpu_rg_addr[ANOC2_STATIC_REGION + NUM_MODEM_MPU_PARTITIONS] = {
57 		{ 0, 0x01e00000, 0x01f00000 },
58 		{ 6, 0x80900000, 0x80b00000 },
59 		{ 7, 0x80860000, 0x80880000 },
60 	};
61 
62 struct rg_domain_ownership gemnoc_cnoc_mpu_rgs[] = {
63 	{ 0, APPS_S_DOMAIN, APPS_NS_DOMAIN | MSA_DOMAIN,
64 	  APPS_NS_DOMAIN | MSA_DOMAIN },
65 	{ 1, APPS_S_DOMAIN, APPS_NS_DOMAIN | MSA_DOMAIN,
66 	  APPS_NS_DOMAIN | MSA_DOMAIN },
67 	{ 2, APPS_S_DOMAIN, APPS_NS_DOMAIN | MSA_DOMAIN,
68 	  APPS_NS_DOMAIN | MSA_DOMAIN },
69 	{ 3, MSA_DOMAIN },
70 	{ 4, APPS_S_DOMAIN, APPS_NS_DOMAIN | MSA_DOMAIN,
71 	  APPS_NS_DOMAIN | MSA_DOMAIN },
72 	{ 5, APPS_S_DOMAIN, APPS_NS_DOMAIN | MSA_DOMAIN,
73 	  APPS_NS_DOMAIN | MSA_DOMAIN },
74 	{ 6, APPS_S_DOMAIN, APPS_NS_DOMAIN | MSA_DOMAIN,
75 	  APPS_NS_DOMAIN | MSA_DOMAIN },
76 	{ 7, APPS_S_DOMAIN, APPS_NS_DOMAIN | MSA_DOMAIN,
77 	  APPS_NS_DOMAIN | MSA_DOMAIN },
78 	{ 8, APPS_S_DOMAIN, APPS_NS_DOMAIN | MSA_DOMAIN,
79 	  APPS_NS_DOMAIN | MSA_DOMAIN },
80 	{ 9, APPS_S_DOMAIN, APPS_NS_DOMAIN | MSA_DOMAIN,
81 	  APPS_NS_DOMAIN | MSA_DOMAIN },
82 	{ 10, APPS_S_DOMAIN, APPS_NS_DOMAIN | MSA_DOMAIN,
83 	  APPS_NS_DOMAIN | MSA_DOMAIN },
84 	{ 11, APPS_S_DOMAIN, APPS_NS_DOMAIN | MSA_DOMAIN,
85 	  APPS_NS_DOMAIN | MSA_DOMAIN },
86 	{ 12, APPS_S_DOMAIN, APPS_NS_DOMAIN | MSA_DOMAIN,
87 	  APPS_NS_DOMAIN | MSA_DOMAIN },
88 	{ 13, APPS_S_DOMAIN, APPS_NS_DOMAIN | MSA_DOMAIN,
89 	  APPS_NS_DOMAIN | MSA_DOMAIN },
90 	{ 14, APPS_S_DOMAIN, APPS_NS_DOMAIN | MSA_DOMAIN,
91 	  APPS_NS_DOMAIN | MSA_DOMAIN },
92 	{ 15, MSA_DOMAIN },
93 	{ 16, APPS_S_DOMAIN, APPS_NS_DOMAIN | MSA_DOMAIN,
94 	  APPS_NS_DOMAIN | MSA_DOMAIN },
95 	{ 17, APPS_S_DOMAIN, APPS_NS_DOMAIN | MSA_DOMAIN,
96 	  APPS_NS_DOMAIN | MSA_DOMAIN },
97 	{ 18, APPS_S_DOMAIN, APPS_NS_DOMAIN | MSA_DOMAIN },
98 	{ 19, APPS_S_DOMAIN, APPS_NS_DOMAIN | MSA_DOMAIN,
99 	  APPS_NS_DOMAIN | MSA_DOMAIN },
100 	{ 23, APPS_S_DOMAIN, APPS_NS_DOMAIN | MSA_DOMAIN, APPS_NS_DOMAIN },
101 	{ 24, APPS_S_DOMAIN, MSA_DOMAIN, MSA_DOMAIN },
102 	{ 25, APPS_S_DOMAIN, MSA_DOMAIN, MSA_DOMAIN },
103 	{ 26, APPS_S_DOMAIN },
104 	{ 27, APPS_S_DOMAIN, 0, APPS_NS_DOMAIN | MSA_DOMAIN },
105 	{ 28, APPS_S_DOMAIN, 0, APPS_NS_DOMAIN | MSA_DOMAIN },
106 	{ 29, APPS_S_DOMAIN },
107 	{ 30, APPS_S_DOMAIN },
108 	{ 31, APPS_S_DOMAIN },
109 	{ 32, APPS_S_DOMAIN },
110 	{ 33, APPS_S_DOMAIN },
111 	{ 34, APPS_S_DOMAIN },
112 	{ 35, APPS_S_DOMAIN },
113 	{ 36, APPS_S_DOMAIN },
114 	{ 37, APPS_S_DOMAIN },
115 	{ 38, APPS_S_DOMAIN },
116 	{ 39, APPS_S_DOMAIN },
117 	{ XPU_UMR_RG, APPS_S_DOMAIN, APPS_NS_DOMAIN, APPS_NS_DOMAIN },
118 };
119 
120 struct rg_partition_range gemnoc_cnoc_mpu_rg_addr[] = {
121 	{ 0, 0x00080000U, 0x05000000U },  { 1, 0x0c310000U, 0x0c3f1000U },
122 	{ 2, 0x00800000U, 0x00b00000U },  { 3, 0x010d2000U, 0x010d3000U },
123 	{ 4, 0x00780000U, 0x007a0000U },  { 5, 0x09000000U, 0x09800000U },
124 	{ 6, 0x0c200000U, 0x0c290000U },  { 7, 0x01520000U, 0x01528000U },
125 	{ 8, 0x01680000U, 0x016b2000U },  { 9, 0x016e0000U, 0x01740000U },
126 	{ 10, 0x01c00000U, 0x01c20000U }, { 11, 0x01e00000U, 0x02000000U },
127 	{ 12, 0x0eff03fcU, 0x0f400000U }, { 13, 0x06000000U, 0x08000000U },
128 	{ 14, 0x0c400000U, 0x0ec00000U }, { 15, 0x010c3000U, 0x010c4000U },
129 	{ 16, 0x0b2c0000U, 0x0b2e0000U }, { 17, 0x0b4c0000U, 0x0b4d0000U },
130 	{ 18, 0x0bbf0000U, 0x0bbf2000U }, { 19, 0x0c2a0000U, 0x0c300000U },
131 	{ 23, 0x0b600000U, 0x0b7f0000U }, { 24, 0x010ca000U, 0x010cc000U },
132 	{ 25, 0x01530000U, 0x01533000U }, { 26, 0xffffffffU, 0xffffffffU },
133 	{ 27, 0x00634000U, 0x00635000U }, { 28, 0x00636000U, 0x00637000U },
134 	{ 29, 0xffffffffU, 0xffffffffU }, { 30, 0xffffffffU, 0xffffffffU },
135 	{ 31, 0xffffffffU, 0xffffffffU }, { 32, 0xffffffffU, 0xffffffffU },
136 	{ 33, 0xffffffffU, 0xffffffffU }, { 34, 0xffffffffU, 0xffffffffU },
137 	{ 35, 0xffffffffU, 0xffffffffU }, { 36, 0xffffffffU, 0xffffffffU },
138 	{ 37, 0xffffffffU, 0xffffffffU }, { 38, 0xffffffffU, 0xffffffffU },
139 	{ 39, 0xffffffffU, 0xffffffffU },
140 };
141 
142 struct rg_partition_range cnoc2_ss_mpu_rg_addr[] = {
143 	{ 0, 0x01680000U, 0x01686000U },  { 1, 0x01686000U, 0x01688000U },
144 	{ 2, 0xffffffffU, 0xffffffffU },  { 3, 0x0168b000U, 0x0168e000U },
145 	{ 4, 0xffffffffU, 0xffffffffU },  { 5, 0x0168e000U, 0x01696000U },
146 	{ 6, 0x01500000U, 0x01506000U },  { 7, 0x01510000U, 0x0151d000U },
147 	{ 8, 0x016e0000U, 0x016e3000U },  { 9, 0x016f2000U, 0x01706000U },
148 	{ 10, 0xffffffffU, 0xffffffffU }, { 11, 0xffffffffU, 0xffffffffU },
149 	{ 12, 0x0170b000U, 0x01710000U }, { 13, 0xffffffffU, 0xffffffffU },
150 	{ 15, 0x0a0cf000U, 0x0a0d0000U }, { 16, 0x01740000U, 0x0174d000U },
151 	{ 17, 0xffffffffU, 0xffffffffU }, { 19, 0x06858000U, 0x06859000U },
152 	{ 20, 0x00100000U, 0x00500000U }, { 21, 0xffffffffU, 0xffffffffU },
153 	{ 22, 0xffffffffU, 0xffffffffU }, { 23, 0xffffffffU, 0xffffffffU },
154 	{ 24, 0x01720000U, 0x01731000U }, { 25, 0xffffffffU, 0xffffffffU },
155 	{ 26, 0x01758000U, 0x01760000U }, { 27, 0x016e6000U, 0x016e7000U },
156 	{ 28, 0x088e2000U, 0x088e3000U }, { 29, 0xffffffffU, 0xffffffffU },
157 	{ 30, 0x000b0000U, 0x000c0000U }, { 31, 0x010d2000U, 0x010d3000U },
158 	{ 32, 0xffffffffU, 0xffffffffU }, { 33, 0xffffffffU, 0xffffffffU },
159 	{ 34, 0x01e00000U, 0x02000000U }, { 35, 0xffffffffU, 0xffffffffU },
160 	{ 36, 0xffffffffU, 0xffffffffU }, { 37, 0x0c310000U, 0x0f400000U },
161 	{ 38, 0x08b1c000U, 0x08b1f000U }, { 39, 0x016a0000U, 0x016b2000U },
162 	{ 40, 0x01522000U, 0x01528000U }, { 41, 0x0152c000U, 0x01533000U },
163 	{ 42, 0xffffffffU, 0xffffffffU }, { 43, 0xffffffffU, 0xffffffffU },
164 	{ 44, 0xffffffffU, 0xffffffffU }, { 45, 0xffffffffU, 0xffffffffU },
165 	{ 46, 0x00634000U, 0x00635000U }, { 47, 0x00636000U, 0x00637000U },
166 };
167 
168 struct rg_domain_ownership cnoc2_ss_mpu_rgs[] = {
169 	{ 0, APPS_S_DOMAIN },
170 	{ 1, MSA_DOMAIN },
171 	{ 2, APPS_S_DOMAIN, APPS_NS_DOMAIN | MSA_DOMAIN,
172 	  MSA_DOMAIN | APPS_NS_DOMAIN },
173 	{ 3, MSA_DOMAIN },
174 	{ 4, APPS_S_DOMAIN },
175 	{ 5, APPS_S_DOMAIN },
176 	{ 6, APPS_S_DOMAIN },
177 	{ 7, APPS_S_DOMAIN },
178 	{ 8, APPS_S_DOMAIN },
179 	{ 9, APPS_S_DOMAIN },
180 	{ 10, APPS_S_DOMAIN },
181 	{ 11, APPS_S_DOMAIN },
182 	{ 12, APPS_S_DOMAIN },
183 	{ 13, APPS_S_DOMAIN },
184 	{ 15, APPS_S_DOMAIN },
185 	{ 16, APPS_S_DOMAIN },
186 	{ 17, MSA_DOMAIN },
187 	{ 19, APPS_S_DOMAIN, APPS_NS_DOMAIN, APPS_NS_DOMAIN },
188 	{ 20, APPS_S_DOMAIN, APPS_NS_DOMAIN | MSA_DOMAIN,
189 	  APPS_NS_DOMAIN | MSA_DOMAIN },
190 	{ 21, APPS_S_DOMAIN },
191 	{ 22, APPS_S_DOMAIN },
192 	{ 23, APPS_S_DOMAIN },
193 	{ 24, APPS_S_DOMAIN },
194 	{ 25, APPS_S_DOMAIN },
195 	{ 26, APPS_S_DOMAIN },
196 	{ 27, APPS_S_DOMAIN },
197 	{ 28, APPS_S_DOMAIN, APPS_NS_DOMAIN, APPS_S_DOMAIN },
198 	{ 29, APPS_S_DOMAIN },
199 	{ 30, MSA_DOMAIN },
200 	{ 31, MSA_DOMAIN },
201 	{ 32, APPS_S_DOMAIN },
202 	{ 33, APPS_S_DOMAIN },
203 	{ 34, APPS_S_DOMAIN, APPS_NS_DOMAIN | MSA_DOMAIN,
204 	  APPS_NS_DOMAIN | MSA_DOMAIN },
205 	{ 35, APPS_S_DOMAIN },
206 	{ 36, APPS_S_DOMAIN },
207 	{ 37, APPS_S_DOMAIN, APPS_NS_DOMAIN | MSA_DOMAIN,
208 	  APPS_NS_DOMAIN | MSA_DOMAIN },
209 	{ 38, APPS_S_DOMAIN },
210 	{ 39, APPS_S_DOMAIN, APPS_NS_DOMAIN | MSA_DOMAIN,
211 	  APPS_NS_DOMAIN | MSA_DOMAIN },
212 	{ 40, APPS_S_DOMAIN, APPS_NS_DOMAIN | MSA_DOMAIN,
213 	  APPS_NS_DOMAIN | MSA_DOMAIN },
214 	{ 41, APPS_S_DOMAIN, APPS_NS_DOMAIN | MSA_DOMAIN,
215 	  APPS_NS_DOMAIN | MSA_DOMAIN },
216 	{ 42, APPS_S_DOMAIN },
217 	{ 43, APPS_S_DOMAIN },
218 	{ 44, APPS_S_DOMAIN },
219 	{ 45, APPS_S_DOMAIN },
220 	{ 46, APPS_S_DOMAIN, 0, APPS_NS_DOMAIN | MSA_DOMAIN },
221 	{ 47, APPS_S_DOMAIN, 0, APPS_NS_DOMAIN | MSA_DOMAIN },
222 };
223 
224 static struct rg_domain_ownership wpss_mpu_rgs[] = {
225 	{ 0, APPS_S_DOMAIN, APPS_NS_DOMAIN, APPS_NS_DOMAIN },
226 	{ 1, APPS_S_DOMAIN, APPS_NS_DOMAIN, APPS_NS_DOMAIN },
227 	{ 2, APPS_S_DOMAIN, APPS_NS_DOMAIN, APPS_NS_DOMAIN },
228 	{ 3, APPS_S_DOMAIN, APPS_NS_DOMAIN, APPS_NS_DOMAIN },
229 	{ 4, APPS_S_DOMAIN, APPS_NS_DOMAIN, APPS_NS_DOMAIN },
230 	{ 5, APPS_S_DOMAIN, APPS_NS_DOMAIN, APPS_NS_DOMAIN },
231 	{ 6, APPS_S_DOMAIN, APPS_NS_DOMAIN, APPS_NS_DOMAIN },
232 	{ 7, APPS_S_DOMAIN, APPS_NS_DOMAIN, APPS_NS_DOMAIN },
233 	{ 8, APPS_S_DOMAIN, APPS_NS_DOMAIN, APPS_NS_DOMAIN },
234 	{ 9, APPS_S_DOMAIN, APPS_NS_DOMAIN, APPS_NS_DOMAIN },
235 	{ 10, APPS_S_DOMAIN, APPS_NS_DOMAIN, APPS_NS_DOMAIN },
236 	{ 11, APPS_S_DOMAIN, APPS_NS_DOMAIN, APPS_NS_DOMAIN },
237 	{ 12, APPS_S_DOMAIN, APPS_NS_DOMAIN, APPS_NS_DOMAIN },
238 	{ 13, APPS_S_DOMAIN, APPS_NS_DOMAIN, APPS_NS_DOMAIN },
239 	{ 14, APPS_S_DOMAIN, APPS_NS_DOMAIN },
240 	{ 15, APPS_S_DOMAIN },
241 	{ 16, APPS_S_DOMAIN, APPS_NS_DOMAIN, APPS_NS_DOMAIN },
242 	{ 17, APPS_S_DOMAIN, APPS_NS_DOMAIN, APPS_NS_DOMAIN },
243 	{ 18, APPS_S_DOMAIN, APPS_NS_DOMAIN },
244 	{ 19, APPS_S_DOMAIN, APPS_NS_DOMAIN },
245 	{ 20, APPS_S_DOMAIN },
246 	{ 21, APPS_S_DOMAIN },
247 	{ 22, APPS_S_DOMAIN },
248 	{ 23, APPS_S_DOMAIN },
249 	{ XPU_UMR_RG, APPS_S_DOMAIN },
250 };
251 
252 static struct rg_partition_range wpss_mpu_addr[] = {
253 	{ 0, 0x80c00000U, 0x81800000U },  { 1, 0x60000000U, 0x64000000U },
254 	{ 2, 0x16000000U, 0x17000000U },  { 3, 0x14680000U, 0x146ab000U },
255 	{ 4, 0x0b2f0000U, 0x0f400000U },  { 5, 0x09200000U, 0x09658000U },
256 	{ 6, 0x091cc000U, 0x091e3000U },  { 7, 0x09080000U, 0x09081000U },
257 	{ 8, 0x00634000U, 0x00635000U },  { 9, 0x06000000U, 0x08000000U },
258 	{ 10, 0x01c00000U, 0x01ff0000U }, { 11, 0x00636000U, 0x00637000U },
259 	{ 12, 0x010dc000U, 0x010dd000U }, { 13, 0x00100000U, 0x004d9000U },
260 	{ 14, 0x004fc000U, 0x004fd000U }, { 15, 0xffffffffU, 0xffffffffU },
261 	{ 16, 0x09ae0000U, 0x09c70000U }, { 17, 0x80900000U, 0x80a0d000U },
262 	{ 18, 0x80aff000U, 0x80b00000U }, { 19, 0x80860000U, 0x80880000U },
263 	{ 20, 0xffffffffU, 0xffffffffU }, { 21, 0xffffffffU, 0xffffffffU },
264 	{ 22, 0xffffffffU, 0xffffffffU }, { 23, 0xffffffffU, 0xffffffffU },
265 };
266 
267 struct rg_domain_ownership aoss_cnoc_mpu_rgs[] = {
268 	{ 24, APPS_S_DOMAIN, APPS_NS_DOMAIN | MSA_DOMAIN,
269 	  APPS_NS_DOMAIN | MSA_DOMAIN },
270 	{ 25, APPS_S_DOMAIN, APPS_NS_DOMAIN | MSA_DOMAIN,
271 	  APPS_NS_DOMAIN | MSA_DOMAIN },
272 	{ 26, NO_DOMAIN, NO_DOMAIN, NO_DOMAIN },
273 	{ 27, NO_DOMAIN, NO_DOMAIN, NO_DOMAIN },
274 	{ 29, APPS_S_DOMAIN, APPS_NS_DOMAIN | MSA_DOMAIN,
275 	  APPS_NS_DOMAIN | MSA_DOMAIN },
276 };
277 
278 struct rg_partition_range aoss_cnoc_mpu_rg_addr[] = {
279 	{ 24, 0x0c200000U, 0x0c210000U }, { 25, 0x0c310000U, 0x0c3f1000U },
280 	{ 26, 0xffffffffU, 0xffffffffU }, { 27, 0xffffffffU, 0xffffffffU },
281 	{ 29, 0x0c400000U, 0x0ec00000U },
282 };
283 
284 struct rg_domain_ownership mss_nav_mpu_rgs[NUM_MSS_NAV_MPU_PARTITIONS + 1] = {
285 	{ XPU_UMR_RG, APPS_NS_DOMAIN },
286 };
287 
288 struct rg_partition_range mss_nav_mpu_rg_addr[NUM_MSS_NAV_MPU_PARTITIONS] = {};
289 
290 struct rg_domain_ownership anoc1_mpu_rgs[NUM_MSS_NAV_MPU_PARTITIONS + 1] = {
291 	{ XPU_UMR_RG, APPS_NS_DOMAIN },
292 };
293 
294 struct rg_partition_range anoc1_mpu_rg_addr[NUM_MSS_NAV_MPU_PARTITIONS] = {};
295 
296 struct rg_domain_ownership modem_ms_mpu_rgs[NUM_MSS_NAV_MPU_PARTITIONS + 1] = {
297 	{ XPU_UMR_RG, APPS_NS_DOMAIN },
298 };
299 
300 struct rg_partition_range modem_ms_mpu_rg_addr[NUM_MSS_NAV_MPU_PARTITIONS] = {};
301 
302 struct xpu_instance msm_xpu_cfg[] = {
303 	{
304 		0x00616000,
305 		ARRAY_SIZE(ramblur_pimem_mpu_rgs),
306 		ramblur_pimem_mpu_rgs,
307 		ARRAY_SIZE(ramblur_pimem_mpu_rg_addr),
308 		ramblur_pimem_mpu_rg_addr,
309 		XPU_TYPE_IMEM_MPU,
310 		XPU_PROTECTION_STATIC,
311 	},
312 	{
313 		0x016a8000,
314 		ANOC2_STATIC_REGION + 1,
315 		anoc2_mpu_rgs,
316 		ANOC2_STATIC_REGION,
317 		anoc2_mpu_rg_addr,
318 		XPU_TYPE_ANOC2_MPU,
319 		XPU_PROTECTION_STATIC,
320 	},
321 	{
322 		0x091fc000,
323 		MSS_Q6_STATIC_REGION + 1,
324 		mss_q6_mpu_rgs,
325 		MSS_Q6_STATIC_REGION,
326 		mss_q6_mpu_rg_addr,
327 		XPU_TYPE_MSS_Q6_MPU,
328 		XPU_PROTECTION_STATIC,
329 	},
330 	{
331 		0x0152c000,
332 		ARRAY_SIZE(gemnoc_cnoc_mpu_rgs),
333 		gemnoc_cnoc_mpu_rgs,
334 		ARRAY_SIZE(gemnoc_cnoc_mpu_rg_addr),
335 		gemnoc_cnoc_mpu_rg_addr,
336 		XPU_TYPE_CNOC_GEMNOC_MPU,
337 		XPU_PROTECTION_STATIC,
338 	},
339 	{
340 		0x01530000,
341 		ARRAY_SIZE(cnoc2_ss_mpu_rgs),
342 		cnoc2_ss_mpu_rgs,
343 		ARRAY_SIZE(cnoc2_ss_mpu_rg_addr),
344 		cnoc2_ss_mpu_rg_addr,
345 		XPU_TYPE_CNOC2_SS_MPU,
346 		XPU_PROTECTION_STATIC,
347 	},
348 	{
349 		0x08b14000,
350 		ARRAY_SIZE(wpss_mpu_rgs),
351 		wpss_mpu_rgs,
352 		ARRAY_SIZE(wpss_mpu_addr),
353 		wpss_mpu_addr,
354 		XPU_TYPE_WPSS_MPU,
355 		XPU_PROTECTION_STATIC,
356 	},
357 	{
358 		0x0eff0000,
359 		ARRAY_SIZE(aoss_cnoc_mpu_rgs),
360 		aoss_cnoc_mpu_rgs,
361 		ARRAY_SIZE(aoss_cnoc_mpu_rg_addr),
362 		aoss_cnoc_mpu_rg_addr,
363 		XPU_TYPE_AOSS_CNOC_MPU,
364 		XPU_PROTECTION_STATIC,
365 	},
366 };
367 
368 const uint32_t msm_xpu_cfg_count = ARRAY_SIZE(msm_xpu_cfg);
369 
370 static struct xpu_instance modem_mpus[] = {
371 	{
372 		0x016a8000,
373 		ARRAY_SIZE(anoc2_mpu_rgs),
374 		anoc2_mpu_rgs,
375 		ARRAY_SIZE(anoc2_mpu_rg_addr),
376 		anoc2_mpu_rg_addr,
377 		XPU_TYPE_ANOC2_MPU,
378 		0,
379 	},
380 	{
381 		0x091fc000,
382 		ARRAY_SIZE(mss_q6_mpu_rgs),
383 		mss_q6_mpu_rgs,
384 		ARRAY_SIZE(mss_q6_mpu_rg_addr),
385 		mss_q6_mpu_rg_addr,
386 		XPU_TYPE_MSS_Q6_MPU,
387 		0,
388 	},
389 };
390 
391 static struct xpu_instance mss_nav_mpus[] = {
392 	{
393 		0x016a0000,
394 		ARRAY_SIZE(mss_nav_mpu_rgs),
395 		mss_nav_mpu_rgs,
396 		ARRAY_SIZE(mss_nav_mpu_rg_addr),
397 		mss_nav_mpu_rg_addr,
398 		XPU_TYPE_MSS_NAV_MPU,
399 		0,
400 	},
401 	{
402 		0x016b0000,
403 		ARRAY_SIZE(anoc1_mpu_rgs),
404 		anoc1_mpu_rgs,
405 		ARRAY_SIZE(anoc1_mpu_rg_addr),
406 		anoc1_mpu_rg_addr,
407 		XPU_TYPE_ANOC1_MPU,
408 		0,
409 	},
410 	{
411 		0x091fe000,
412 		ARRAY_SIZE(modem_ms_mpu_rgs),
413 		modem_ms_mpu_rgs,
414 		ARRAY_SIZE(modem_ms_mpu_rg_addr),
415 		modem_ms_mpu_rg_addr,
416 		XPU_TYPE_MSS_MPU,
417 		0,
418 	},
419 };
420 
421 struct mpu_ranges msm_mpu_ranges[] = {
422 	{
423 		DEVICE_MODEM,
424 		ARRAY_SIZE(modem_mpus),
425 		NUM_MODEM_MPU_PARTITIONS,
426 		modem_mpus,
427 	},
428 	{
429 		DEVICE_MSS_NAV,
430 		ARRAY_SIZE(mss_nav_mpus),
431 		NUM_MSS_NAV_MPU_PARTITIONS,
432 		mss_nav_mpus,
433 	},
434 };
435 
436 const uint32_t msm_mpu_ranges_count = ARRAY_SIZE(msm_mpu_ranges);
437