1 /* 2 * Copyright (c) 2018-2022, Arm Limited and Contributors. All rights reserved. 3 * Copyright (c) 2019-2022, Xilinx, Inc. All rights reserved. 4 * Copyright (c) 2022-2024, Advanced Micro Devices, Inc. All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef VERSAL_DEF_H 10 #define VERSAL_DEF_H 11 12 #include <plat/arm/common/smccc_def.h> 13 #include <plat/common/common_def.h> 14 15 #define PLATFORM_MASK GENMASK(27U, 24U) 16 #define PLATFORM_VERSION_MASK GENMASK(31U, 28U) 17 18 /* number of interrupt handlers. increase as required */ 19 #define MAX_INTR_EL3 2U 20 /* List all consoles */ 21 #define VERSAL_CONSOLE_ID_none 0 22 #define VERSAL_CONSOLE_ID_pl011 1 23 #define VERSAL_CONSOLE_ID_pl011_0 1 24 #define VERSAL_CONSOLE_ID_pl011_1 2 25 #define VERSAL_CONSOLE_ID_dcc 3 26 #define VERSAL_CONSOLE_ID_dtb 4 27 28 #define CONSOLE_IS(con) (VERSAL_CONSOLE_ID_ ## con == VERSAL_CONSOLE) 29 30 /* Runtime console */ 31 #define RT_CONSOLE_ID_pl011 1 32 #define RT_CONSOLE_ID_pl011_0 1 33 #define RT_CONSOLE_ID_pl011_1 2 34 #define RT_CONSOLE_ID_dcc 3 35 #define RT_CONSOLE_ID_dtb 4 36 37 #define RT_CONSOLE_IS(con) (RT_CONSOLE_ID_ ## con == CONSOLE_RUNTIME) 38 39 /* List of platforms */ 40 #define VERSAL_SILICON 0U 41 #define VERSAL_SPP 1U 42 #define VERSAL_EMU 2U 43 #define VERSAL_QEMU 3U 44 #define VERSAL_COSIM 7U 45 46 #define PMC_TAP_VERSION U(0xF11A0004) 47 48 /* Firmware Image Package */ 49 #define VERSAL_PRIMARY_CPU 0 50 51 /******************************************************************************* 52 * memory map related constants 53 ******************************************************************************/ 54 #define DEVICE0_BASE U(0xFF000000) 55 #define DEVICE0_SIZE U(0x00E00000) 56 #define DEVICE1_BASE U(0xF9000000) 57 #define DEVICE1_SIZE U(0x00800000) 58 59 /******************************************************************************* 60 * IRQ constants 61 ******************************************************************************/ 62 #define VERSAL_IRQ_SEC_PHY_TIMER 29U 63 #define ARM_IRQ_SEC_PHY_TIMER 29 64 65 /******************************************************************************* 66 * CCI-400 related constants 67 ******************************************************************************/ 68 #define PLAT_ARM_CCI_BASE UL(0xFD000000) 69 #define PLAT_ARM_CCI_SIZE U(0x00100000) 70 #define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 4 71 #define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 5 72 73 /******************************************************************************* 74 * UART related constants 75 ******************************************************************************/ 76 #define VERSAL_UART0_BASE U(0xFF000000) 77 #define VERSAL_UART1_BASE U(0xFF010000) 78 79 #if CONSOLE_IS(pl011) || CONSOLE_IS(dtb) 80 # define UART_BASE VERSAL_UART0_BASE 81 # define UART_TYPE CONSOLE_PL011 82 #elif CONSOLE_IS(pl011_1) 83 # define UART_BASE VERSAL_UART1_BASE 84 # define UART_TYPE CONSOLE_PL011 85 #elif CONSOLE_IS(dcc) 86 # define UART_BASE 0x0 87 # define UART_TYPE CONSOLE_DCC 88 #elif CONSOLE_IS(none) 89 # define UART_TYPE CONSOLE_NONE 90 #else 91 # error "invalid VERSAL_CONSOLE" 92 #endif 93 94 /* Runtime console */ 95 #if defined(CONSOLE_RUNTIME) 96 #if RT_CONSOLE_IS(pl011) || RT_CONSOLE_IS(dtb) 97 # define RT_UART_BASE VERSAL_UART0_BASE 98 # define RT_UART_TYPE CONSOLE_PL011 99 #elif RT_CONSOLE_IS(pl011_1) 100 # define RT_UART_BASE VERSAL_UART1_BASE 101 # define RT_UART_TYPE CONSOLE_PL011 102 #elif RT_CONSOLE_IS(dcc) 103 # define RT_UART_BASE 0x0 104 # define RT_UART_TYPE CONSOLE_DCC 105 #else 106 # error "invalid CONSOLE_RUNTIME" 107 #endif 108 #endif 109 110 /******************************************************************************* 111 * Platform related constants 112 ******************************************************************************/ 113 #define UART_BAUDRATE 115200 114 115 /* Access control register defines */ 116 #define ACTLR_EL3_L2ACTLR_BIT (1U << 6) 117 #define ACTLR_EL3_CPUACTLR_BIT (1U << 0) 118 119 /* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/ 120 #define CRF_BASE U(0xFD1A0000) 121 #define CRF_SIZE U(0x00600000) 122 123 /* CRF registers and bitfields */ 124 #define CRF_RST_APU (CRF_BASE + 0X00000300) 125 126 #define CRF_RST_APU_ACPU_RESET (1U << 0) 127 #define CRF_RST_APU_ACPU_PWRON_RESET (1U << 10) 128 129 /* IOU SCNTRS */ 130 #define IOU_SCNTRS_BASE U(0xFF140000) 131 #define IOU_SCNTRS_BASE_FREQ_OFFSET 0x20U 132 133 /* APU registers and bitfields */ 134 #define FPD_APU_BASE 0xFD5C0000U 135 #define FPD_APU_CONFIG_0 (FPD_APU_BASE + 0x20U) 136 #define FPD_APU_RVBAR_L_0 (FPD_APU_BASE + 0x40U) 137 #define FPD_APU_RVBAR_H_0 (FPD_APU_BASE + 0x44U) 138 #define FPD_APU_PWRCTL (FPD_APU_BASE + 0x90U) 139 140 #define FPD_APU_CONFIG_0_VINITHI_SHIFT 8U 141 #define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1U 142 #define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2U 143 144 /* PMC registers and bitfields */ 145 #define PMC_GLOBAL_BASE 0xF1110000U 146 #define PMC_GLOBAL_GLOB_GEN_STORAGE4 (PMC_GLOBAL_BASE + 0x40U) 147 148 #endif /* VERSAL_DEF_H */ 149