1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Rockchip Vehicle driver 4 * 5 * Copyright (C) 2022 Rockchip Electronics Co., Ltd. 6 * 7 */ 8 9 #ifndef _VEHICLE_SAMSUNG_DCPHY_COMMON_H_ 10 #define _VEHICLE_SAMSUNG_DCPHY_COMMON_H_ 11 12 #define MAX_NUM_CSI2_DPHY (0x2) 13 14 /*redefine samsung_mipi_dcphy info*/ 15 struct samsung_mipi_dcphy { 16 struct device *dev; 17 struct clk *ref_clk; 18 struct clk *pclk; 19 struct regmap *regmap; 20 struct regmap *grf_regmap; 21 struct reset_control *m_phy_rst; 22 struct reset_control *s_phy_rst; 23 struct reset_control *apb_rst; 24 struct reset_control *grf_apb_rst; 25 struct mutex mutex; 26 struct csi2_dphy *dphy_dev[MAX_NUM_CSI2_DPHY]; 27 atomic_t stream_cnt; 28 int dphy_dev_num; 29 bool c_option; 30 31 unsigned int lanes; 32 33 struct { 34 unsigned long long rate; 35 u8 prediv; 36 u16 fbdiv; 37 long dsm; 38 u8 scaler; 39 40 bool ssc_en; 41 u8 mfr; 42 u8 mrr; 43 } pll; 44 45 int (*stream_on)(struct csi2_dphy *dphy, struct v4l2_subdev *sd); 46 int (*stream_off)(struct csi2_dphy *dphy, struct v4l2_subdev *sd); 47 48 /*for vehicle*/ 49 struct csi2_dphy_hw *dphy_vehicle[MAX_NUM_CSI2_DPHY]; 50 int dphy_vehicle_num; 51 }; 52 53 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) 54 55 /*samsung mipi dcphy register*/ 56 #define BIAS_CON0 0x0000 57 #define BIAS_CON1 0x0004 58 #define BIAS_CON2 0x0008 59 #define BIAS_CON4 0x0010 60 #define I_MUX_SEL_MASK GENMASK(6, 5) 61 #define I_MUX_SEL(x) UPDATE(x, 6, 5) 62 63 #define PLL_CON0 0x0100 64 #define PLL_EN BIT(12) 65 #define S_MASK GENMASK(10, 8) 66 #define S(x) UPDATE(x, 10, 8) 67 #define P_MASK GENMASK(5, 0) 68 #define P(x) UPDATE(x, 5, 0) 69 #define PLL_CON1 0x0104 70 #define PLL_CON2 0x0108 71 #define M_MASK GENMASK(9, 0) 72 #define M(x) UPDATE(x, 9, 0) 73 #define PLL_CON3 0x010c 74 #define MRR_MASK GENMASK(13, 8) 75 #define MRR(x) UPDATE(x, 13, 8) 76 #define MFR_MASK GENMASK(7, 0) 77 #define MFR(x) UPDATE(x, 7, 0) 78 #define PLL_CON4 0x0110 79 #define SSCG_EN BIT(11) 80 #define PLL_CON5 0x0114 81 #define RESET_N_SEL BIT(10) 82 #define PLL_ENABLE_SEL BIT(8) 83 #define PLL_CON6 0x0118 84 #define PLL_CON7 0x011c 85 #define PLL_LOCK_CNT(x) UPDATE(x, 15, 0) 86 #define PLL_CON8 0x0120 87 #define PLL_STB_CNT(x) UPDATE(x, 15, 0) 88 #define PLL_STAT0 0x0140 89 #define PLL_LOCK BIT(0) 90 91 #define DPHY_MC_GNR_CON0 0x0300 92 #define PHY_READY BIT(1) 93 #define PHY_ENABLE BIT(0) 94 #define DPHY_MC_GNR_CON1 0x0304 95 #define T_PHY_READY(x) UPDATE(x, 15, 0) 96 #define DPHY_MC_ANA_CON0 0x0308 97 #define DPHY_MC_ANA_CON1 0x030c 98 #define DPHY_MC_ANA_CON2 0x0310 99 #define HS_VREG_AMP_ICON(x) UPDATE(x, 1, 0) 100 #define DPHY_MC_TIME_CON0 0x0330 101 #define HSTX_CLK_SEL BIT(12) 102 #define T_LPX(x) UPDATE(x, 11, 4) 103 #define DPHY_MC_TIME_CON1 0x0334 104 #define T_CLK_ZERO(x) UPDATE(x, 15, 8) 105 #define T_CLK_PREPARE(x) UPDATE(x, 7, 0) 106 #define DPHY_MC_TIME_CON2 0x0338 107 #define T_HS_EXIT(x) UPDATE(x, 15, 8) 108 #define T_CLK_TRAIL(x) UPDATE(x, 7, 0) 109 #define DPHY_MC_TIME_CON3 0x033c 110 #define T_CLK_POST(x) UPDATE(x, 7, 0) 111 #define DPHY_MC_TIME_CON4 0x0340 112 #define T_ULPS_EXIT(x) UPDATE(x, 9, 0) 113 #define DPHY_MC_DESKEW_CON0 0x0350 114 #define SKEW_CAL_RUN_TIME(x) UPDATE(x, 15, 12) 115 116 #define SKEW_CAL_INIT_RUN_TIME(x) UPDATE(x, 11, 8) 117 #define SKEW_CAL_INIT_WAIT_TIME(x) UPDATE(x, 7, 4) 118 #define SKEW_CAL_EN BIT(0) 119 120 #define COMBO_MD0_GNR_CON0 0x0400 121 #define COMBO_MD0_GNR_CON1 0x0404 122 #define COMBO_MD0_ANA_CON0 0x0408 123 #define COMBO_MD0_ANA_CON1 0x040C 124 #define COMBO_MD0_ANA_CON2 0x0410 125 126 #define COMBO_MD0_TIME_CON0 0x0430 127 #define COMBO_MD0_TIME_CON1 0x0434 128 #define COMBO_MD0_TIME_CON2 0x0438 129 #define COMBO_MD0_TIME_CON3 0x043C 130 #define COMBO_MD0_TIME_CON4 0x0440 131 #define COMBO_MD0_DATA_CON0 0x0444 132 133 #define COMBO_MD1_GNR_CON0 0x0500 134 #define COMBO_MD1_GNR_CON1 0x0504 135 #define COMBO_MD1_ANA_CON0 0x0508 136 #define COMBO_MD1_ANA_CON1 0x050c 137 #define COMBO_MD1_ANA_CON2 0x0510 138 #define COMBO_MD1_TIME_CON0 0x0530 139 #define COMBO_MD1_TIME_CON1 0x0534 140 #define COMBO_MD1_TIME_CON2 0x0538 141 #define COMBO_MD1_TIME_CON3 0x053C 142 #define COMBO_MD1_TIME_CON4 0x0540 143 #define COMBO_MD1_DATA_CON0 0x0544 144 145 #define COMBO_MD2_GNR_CON0 0x0600 146 #define COMBO_MD2_GNR_CON1 0x0604 147 #define COMBO_MD2_ANA_CON0 0X0608 148 #define COMBO_MD2_ANA_CON1 0X060C 149 #define COMBO_MD2_ANA_CON2 0X0610 150 #define COMBO_MD2_TIME_CON0 0x0630 151 #define COMBO_MD2_TIME_CON1 0x0634 152 #define COMBO_MD2_TIME_CON2 0x0638 153 #define COMBO_MD2_TIME_CON3 0x063C 154 #define COMBO_MD2_TIME_CON4 0x0640 155 #define COMBO_MD2_DATA_CON0 0x0644 156 157 #define DPHY_MD3_GNR_CON0 0x0700 158 #define DPHY_MD3_GNR_CON1 0x0704 159 #define DPHY_MD3_ANA_CON0 0X0708 160 #define DPHY_MD3_ANA_CON1 0X070C 161 #define DPHY_MD3_ANA_CON2 0X0710 162 #define DPHY_MD3_TIME_CON0 0x0730 163 #define DPHY_MD3_TIME_CON1 0x0734 164 #define DPHY_MD3_TIME_CON2 0x0738 165 #define DPHY_MD3_TIME_CON3 0x073C 166 #define DPHY_MD3_TIME_CON4 0x0740 167 #define DPHY_MD3_DATA_CON0 0x0744 168 169 #define T_LP_EXIT_SKEW(x) UPDATE(x, 3, 2) 170 #define T_LP_ENTRY_SKEW(x) UPDATE(x, 1, 0) 171 #define T_HS_ZERO(x) UPDATE(x, 15, 8) 172 #define T_HS_PREPARE(x) UPDATE(x, 7, 0) 173 #define T_HS_EXIT(x) UPDATE(x, 15, 8) 174 #define T_HS_TRAIL(x) UPDATE(x, 7, 0) 175 #define T_TA_GET(x) UPDATE(x, 7, 4) 176 #define T_TA_GO(x) UPDATE(x, 3, 0) 177 178 /* MIPI_CDPHY_GRF registers */ 179 #define MIPI_DCPHY_GRF_CON0 0x0000 180 #define S_CPHY_MODE HIWORD_UPDATE(1, 3, 3) 181 #define M_CPHY_MODE HIWORD_UPDATE(1, 0, 0) 182 183 #define MAX_DPHY_BW 4500000L 184 #define MAX_CPHY_BW 2000000L 185 186 #define RX_CLK_THS_SETTLE (0xb30) 187 #define RX_LANE0_THS_SETTLE (0xC30) 188 #define RX_LANE0_ERR_SOT_SYNC (0xC34) 189 #define RX_LANE1_THS_SETTLE (0xD30) 190 #define RX_LANE1_ERR_SOT_SYNC (0xD34) 191 #define RX_LANE2_THS_SETTLE (0xE30) 192 #define RX_LANE2_ERR_SOT_SYNC (0xE34) 193 #define RX_LANE3_THS_SETTLE (0xF30) 194 #define RX_LANE3_ERR_SOT_SYNC (0xF34) 195 #define RX_CLK_LANE_ENABLE (0xB00) 196 #define RX_DATA_LANE0_ENABLE (0xC00) 197 #define RX_DATA_LANE1_ENABLE (0xD00) 198 #define RX_DATA_LANE2_ENABLE (0xE00) 199 #define RX_DATA_LANE3_ENABLE (0xF00) 200 201 #define RX_S0C_GNR_CON1 (0xB04) 202 #define RX_S0C_ANA_CON1 (0xB0c) 203 #define RX_S0C_ANA_CON2 (0xB10) 204 #define RX_S0C_ANA_CON3 (0xB14) 205 #define RX_COMBO_S0D0_GNR_CON1 (0xC04) 206 #define RX_COMBO_S0D0_ANA_CON1 (0xC0c) 207 #define RX_COMBO_S0D0_ANA_CON2 (0xC10) 208 #define RX_COMBO_S0D0_ANA_CON3 (0xC14) 209 #define RX_COMBO_S0D0_ANA_CON6 (0xC20) 210 #define RX_COMBO_S0D0_ANA_CON7 (0xC24) 211 #define RX_COMBO_S0D0_DESKEW_CON0 (0xC40) 212 #define RX_COMBO_S0D0_DESKEW_CON2 (0xC48) 213 #define RX_COMBO_S0D0_DESKEW_CON4 (0xC50) 214 #define RX_COMBO_S0D0_CRC_CON1 (0xC64) 215 #define RX_COMBO_S0D0_CRC_CON2 (0xC68) 216 #define RX_COMBO_S0D1_GNR_CON1 (0xD04) 217 #define RX_COMBO_S0D1_ANA_CON1 (0xD0c) 218 #define RX_COMBO_S0D1_ANA_CON2 (0xD10) 219 #define RX_COMBO_S0D1_ANA_CON3 (0xD14) 220 #define RX_COMBO_S0D1_ANA_CON6 (0xD20) 221 #define RX_COMBO_S0D1_ANA_CON7 (0xD24) 222 #define RX_COMBO_S0D1_DESKEW_CON0 (0xD40) 223 #define RX_COMBO_S0D1_DESKEW_CON2 (0xD48) 224 #define RX_COMBO_S0D1_DESKEW_CON4 (0xD50) 225 #define RX_COMBO_S0D1_CRC_CON1 (0xD64) 226 #define RX_COMBO_S0D1_CRC_CON2 (0xD68) 227 #define RX_COMBO_S0D2_GNR_CON1 (0xE04) 228 #define RX_COMBO_S0D2_ANA_CON1 (0xE0c) 229 #define RX_COMBO_S0D2_ANA_CON2 (0xE10) 230 #define RX_COMBO_S0D2_ANA_CON3 (0xE14) 231 #define RX_COMBO_S0D2_ANA_CON6 (0xE20) 232 #define RX_COMBO_S0D2_ANA_CON7 (0xE24) 233 #define RX_COMBO_S0D2_DESKEW_CON0 (0xE40) 234 #define RX_COMBO_S0D2_DESKEW_CON2 (0xE48) 235 #define RX_COMBO_S0D2_DESKEW_CON4 (0xE50) 236 #define RX_COMBO_S0D2_CRC_CON1 (0xE64) 237 #define RX_COMBO_S0D2_CRC_CON2 (0xE68) 238 #define RX_S0D3_GNR_CON1 (0xF04) 239 #define RX_S0D3_ANA_CON1 (0xF0c) 240 #define RX_S0D3_ANA_CON2 (0xF10) 241 #define RX_S0D3_ANA_CON3 (0xF14) 242 #define RX_S0D3_DESKEW_CON0 (0xF40) 243 #define RX_S0D3_DESKEW_CON2 (0xF48) 244 #define RX_S0D3_DESKEW_CON4 (0xF50) 245 246 #endif 247