1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 //////////////////////////////////////////////////////////////////////////////// 79 // 80 // Copyright (c) 2008-2009 MStar Semiconductor, Inc. 81 // All rights reserved. 82 // 83 // Unless otherwise stipulated in writing, any and all information contained 84 // herein regardless in any format shall remain the sole proprietary of 85 // MStar Semiconductor Inc. and be kept in strict confidence 86 // ("MStar Confidential Information") by the recipient. 87 // Any unauthorized act including without limitation unauthorized disclosure, 88 // copying, use, reproduction, sale, distribution, modification, disassembling, 89 // reverse engineering and compiling of the contents of MStar Confidential 90 // Information is unlawful and strictly prohibited. MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 #ifndef _HWREG_UTILITY_H_ 95 #define _HWREG_UTILITY_H_ 96 97 #include "ve_hwreg.h" 98 #include "MsCommon.h" 99 100 //!! Do not include this header in driver or api level 101 102 //------------------------------------------------------------------------------------------------- 103 // Macro and Define 104 //------------------------------------------------------------------------------------------------- 105 extern MS_VIRT _VE_RIU_BASE; // This should be inited before XC library starting. 106 extern MS_BOOL g_bVeDisableRegWrite; 107 108 #define _BITMASK(loc_msb, loc_lsb) ((1U << (loc_msb)) - (1U << (loc_lsb)) + (1U << (loc_msb))) 109 #define BITMASK(x) _BITMASK(1?x, 0?x) 110 #define HBMASK 0xFF00 111 #define LBMASK 0x00FF 112 113 #define RIU_MACRO_START do { 114 #define RIU_MACRO_END } while (0) 115 116 // Address bus of RIU is 16 bits. 117 #define RIU_READ_BYTE(addr) ( READ_BYTE( _VE_RIU_BASE + (addr) ) ) 118 #define RIU_READ_2BYTE(addr) ( READ_WORD( _VE_RIU_BASE + (addr) ) ) 119 #define RIU_WRITE_BYTE(addr, val) { WRITE_BYTE( _VE_RIU_BASE + (addr), val) } 120 #define RIU_WRITE_2BYTE(addr, val) { WRITE_WORD( _VE_RIU_BASE + (addr), val) } 121 122 123 //============================================================= 124 // Standard Form 125 126 #define MDrv_ReadByte( u32Reg ) RIU_READ_BYTE(((u32Reg) << 1) - ((u32Reg) & 1)) 127 128 #define MDrv_Read2Byte( u32Reg ) (RIU_READ_2BYTE((u32Reg)<<1)) 129 130 #define MDrv_Read4Byte( u32Reg ) ( (MS_U32)RIU_READ_2BYTE((u32Reg)<<1) | ((MS_U32)RIU_READ_2BYTE(((u32Reg)+2)<<1)<<16 ) ) 131 132 #define MDrv_ReadRegBit( u32Reg, u8Mask ) (RIU_READ_BYTE(((u32Reg)<<1) - ((u32Reg) & 1)) & (u8Mask)) 133 134 #define MDrv_WriteRegBit( u32Reg, bEnable, u8Mask ) \ 135 RIU_MACRO_START \ 136 if(g_bVeDisableRegWrite == TRUE) \ 137 { \ 138 break; \ 139 } \ 140 RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) , (bEnable) ? (RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) | (u8Mask)) : \ 141 (RIU_READ_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)) ) & ~(u8Mask))); \ 142 RIU_MACRO_END 143 144 #define MDrv_WriteByte( u32Reg, u8Val ) \ 145 RIU_MACRO_START \ 146 if(g_bVeDisableRegWrite == TRUE) \ 147 { \ 148 break; \ 149 } \ 150 RIU_WRITE_BYTE(((u32Reg) << 1) - ((u32Reg) & 1), u8Val); \ 151 RIU_MACRO_END 152 153 #define MDrv_Write2Byte( u32Reg, u16Val ) \ 154 RIU_MACRO_START \ 155 if(g_bVeDisableRegWrite == TRUE) \ 156 { \ 157 break; \ 158 } \ 159 if ( ((u32Reg) & 0x01) ) \ 160 { \ 161 RIU_WRITE_BYTE(((u32Reg) << 1) - 1, (MS_U8)((u16Val))); \ 162 RIU_WRITE_BYTE(((u32Reg) + 1) << 1, (MS_U8)((u16Val) >> 8)); \ 163 } \ 164 else \ 165 { \ 166 RIU_WRITE_2BYTE( ((u32Reg)<<1) , u16Val); \ 167 } \ 168 RIU_MACRO_END 169 170 #define MDrv_Write3Byte( u32Reg, u32Val ) \ 171 RIU_MACRO_START \ 172 if(g_bVeDisableRegWrite == TRUE) \ 173 { \ 174 break; \ 175 } \ 176 if ((u32Reg) & 0x01) \ 177 { \ 178 RIU_WRITE_BYTE((u32Reg << 1) - 1, u32Val); \ 179 RIU_WRITE_2BYTE( (u32Reg + 1)<<1 , ((u32Val) >> 8)); \ 180 } \ 181 else \ 182 { \ 183 RIU_WRITE_2BYTE( (u32Reg) << 1, u32Val); \ 184 RIU_WRITE_BYTE( (u32Reg + 2) << 1 , ((u32Val) >> 16)); \ 185 } \ 186 RIU_MACRO_END 187 188 #define MDrv_Write4Byte( u32Reg, u32Val ) \ 189 RIU_MACRO_START \ 190 if(g_bVeDisableRegWrite == TRUE) \ 191 { \ 192 break; \ 193 } \ 194 if ((u32Reg) & 0x01) \ 195 { \ 196 RIU_WRITE_BYTE( ((u32Reg) << 1) - 1 , u32Val); \ 197 RIU_WRITE_2BYTE( ((u32Reg) + 1)<<1 , ( (u32Val) >> 8)); \ 198 RIU_WRITE_BYTE( (((u32Reg) + 3) << 1) , ((u32Val) >> 24)); \ 199 } \ 200 else \ 201 { \ 202 RIU_WRITE_2BYTE( (u32Reg) <<1 , u32Val); \ 203 RIU_WRITE_2BYTE( ((u32Reg) + 2)<<1 , ((u32Val) >> 16)); \ 204 } \ 205 RIU_MACRO_END 206 207 #define MDrv_WriteByteMask( u32Reg, u8Val, u8Msk ) \ 208 RIU_MACRO_START \ 209 if(g_bVeDisableRegWrite == TRUE) \ 210 { \ 211 break; \ 212 } \ 213 RIU_WRITE_BYTE( (((u32Reg) <<1) - ((u32Reg) & 1)), (RIU_READ_BYTE((((u32Reg) <<1) - ((u32Reg) & 1))) & ~(u8Msk)) | ((u8Val) & (u8Msk))); \ 214 RIU_MACRO_END 215 216 #define MDrv_Write2ByteMask( u32Reg, u16Val, u16Mask) \ 217 RIU_MACRO_START \ 218 if(g_bVeDisableRegWrite == TRUE) \ 219 { \ 220 break; \ 221 } \ 222 RIU_WRITE_2BYTE(u32Reg<<1, (RIU_READ_2BYTE(u32Reg<<1) & ~(u16Mask)) | (u16Val & u16Mask)) \ 223 RIU_MACRO_END 224 225 226 //============================================================ 227 // For Dump Table 228 // u32Addr must be 16bit aligned 229 #define READ2BYTE(u32Addr, u16mask) \ 230 (READ_WORD (_VE_RIU_BASE + (u32Addr << 1)) & BMASK(u16mask)) 231 232 // u32Addr must be 16bit aligned 233 #define W2BYTE_TAB(u32Addr, u16Val, u16mask) \ 234 (WRITE_WORD(_VE_RIU_BASE + ( (u32Addr) << 1), (READ2BYTE( (u32Addr) , 15:0) & ~u16mask) | ( (u16Val) & u16mask))) 235 236 237 //============================================================= 238 // Just for Scaler 239 #define SC_W2BYTE( u32Reg, u16Val)\ 240 ( { RIU_WRITE_2BYTE(REG_SCALER_BASE << 1, ((u32Reg) >> 8) & 0x00FF ) ; \ 241 RIU_WRITE_2BYTE( (REG_SCALER_BASE +((u32Reg) & 0xFF) ) << 1 , u16Val ) ; } ) 242 243 #define SC_R2BYTE( u32Reg ) \ 244 ( { RIU_WRITE_2BYTE(REG_SCALER_BASE << 1, ( (u32Reg) >> 8) & 0x00FF ) ; \ 245 RIU_READ_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFF) )<<1 ) ; } ) 246 247 #define SC_W4BYTE( u32Reg, u32Val)\ 248 ( { RIU_WRITE_2BYTE(REG_SCALER_BASE<<1, ((u32Reg) >> 8) & 0x00FF ) ; \ 249 RIU_WRITE_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFF) ) <<1, (MS_U16)((u32Val) & 0x0000FFFF) ) ; \ 250 RIU_WRITE_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFF) + 2 ) << 1, (MS_U16)(((u32Val) >> 16) & 0x0000FFFF) ); } ) 251 252 #define SC_R4BYTE( u32Reg )\ 253 ( { RIU_WRITE_2BYTE(REG_SCALER_BASE << 1, ((u32Reg) >> 8) & 0x00FF ) ; \ 254 RIU_READ_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFF) ) << 1 ) | (MS_U32)(RIU_READ_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFF) + 2 ) << 1 )) << 16; } ) 255 256 #define SC_R2BYTEMSK( u32Reg, u16mask)\ 257 ( { RIU_WRITE_2BYTE(REG_SCALER_BASE << 1, ((u32Reg) >> 8) & 0x00FF ) ; \ 258 RIU_READ_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFF) ) << 1) & (u16mask) ; } ) 259 260 #define SC_W2BYTEMSK( u32Reg, u16Val, u16Mask)\ 261 ( { RIU_WRITE_2BYTE(REG_SCALER_BASE << 1, ((u32Reg) >> 8) & 0x00FF ) ; \ 262 RIU_WRITE_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFF) ) << 1, (RIU_READ_2BYTE( (REG_SCALER_BASE + ((u32Reg) & 0xFF) ) << 1) & ~(u16Mask) ) | ((u16Val) & (u16Mask)) ) ; }) 263 264 //============================================================= 265 // Just for MOD 266 #define MOD_W2BYTE( u32Reg, u16Val)\ 267 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \ 268 RIU_WRITE_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1, u16Val ); } ) 269 270 #define MOD_R2BYTE( u32Reg ) \ 271 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \ 272 RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1) ; } ) 273 274 #define MOD_R2BYTEMSK( u32Reg, u16mask)\ 275 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \ 276 RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1) & (u16mask); }) 277 278 #define MOD_W2BYTEMSK( u32Reg, u16Val, u16Mask)\ 279 ( { RIU_WRITE_2BYTE(REG_MOD_BASE << 1, ((u32Reg) >> 8) & 0x00FF ); \ 280 RIU_WRITE_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) )<<1 , (RIU_READ_2BYTE( (REG_MOD_BASE + ((u32Reg) & 0xFF) ) << 1 ) & ~(u16Mask)) | ((u16Val) & (u16Mask)) ); } ) 281 282 283 //============================================================= 284 //General ( Make sure u32Reg is not ODD 285 #define W2BYTE( u32Reg, u16Val) RIU_WRITE_2BYTE( (u32Reg) << 1 , u16Val ) 286 287 288 #define R2BYTE( u32Reg ) RIU_READ_2BYTE( (u32Reg) << 1) 289 290 #define W4BYTE( u32Reg, u32Val)\ 291 ( { RIU_WRITE_2BYTE( (u32Reg) << 1, ((u32Val) & 0x0000FFFF) ); \ 292 RIU_WRITE_2BYTE( ( (u32Reg) + 2) << 1 , (((u32Val) >> 16) & 0x0000FFFF)) ; } ) 293 294 #define R4BYTE( u32Reg )\ 295 ( { ((RIU_READ_2BYTE( (u32Reg) << 1)) | ((MS_U32)(RIU_READ_2BYTE( ( (u32Reg) + 2 ) << 1) ) << 16)) ; } ) 296 297 #define R2BYTEMSK( u32Reg, u16mask)\ 298 ( { RIU_READ_2BYTE( (u32Reg)<< 1) & (u16mask) ; } ) 299 300 #define W2BYTEMSK( u32Reg, u16Val, u16Mask)\ 301 ( { RIU_WRITE_2BYTE( (u32Reg)<< 1 , (RIU_READ_2BYTE((u32Reg) << 1) & ~(u16Mask)) | ((u16Val) & (u16Mask)) ) ; } ) 302 303 304 //------------------------------------------------------------------------------------------------- 305 // Type and Structure 306 //------------------------------------------------------------------------------------------------- 307 308 309 //------------------------------------------------------------------------------------------------- 310 // Function and Variable 311 //------------------------------------------------------------------------------------------------- 312 313 314 #endif 315 316