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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef VE_ANALOG_REG_H 96 #define VE_ANALOG_REG_H 97 98 #include "ve_hwreg.h" 99 /******************************************************************************/ 100 /* Macro */ 101 /******************************************************************************/ 102 103 #ifndef UNUSED 104 #define UNUSED(x) ((x)=(x)) 105 #endif 106 107 /////////////////////////////////////////////////////// 108 // Scaler Bank 109 /////////////////////////////////////////////////////// 110 111 #define HIPART( u32x ) (((u32x) >> 16) & 0xFFFF) 112 #define LOPART( u32x ) ((u32x) & 0xFFFF) 113 114 #define BK_REG_L( x, y ) ((x) | (((y) << 1))) 115 #define BK_REG_H( x, y ) (((x) | (((y) << 1))) + 1) 116 117 /* Component */ 118 #define L_BK_COMPONENT(x) BK_REG_L(REG_BASE_COMPONENT, x) 119 #define H_BK_COMPONENT(x) BK_REG_H(REG_BASE_COMPONENT, x) 120 121 /* VE */ 122 #define L_BK_VE_ENC_EX(x) BK_REG_L(REG_BASE_VE_ENCODER_EX, x) 123 #define H_BK_VE_ENC_EX(x) BK_REG_H(REG_BASE_VE_ENCODER_EX, x) 124 #define L_BK_VE_ENC(x) BK_REG_L(REG_BASE_VE_ENCODER, x) 125 #define H_BK_VE_ENC(x) BK_REG_H(REG_BASE_VE_ENCODER, x) 126 #define L_BK_VE_SRC(x) BK_REG_L(REG_BASE_VE_SOURCE, x) 127 #define H_BK_VE_SRC(x) BK_REG_H(REG_BASE_VE_SOURCE, x) 128 #define L_BK_VE_DISC(x) BK_REG_L(REG_BASE_VE_DISC, x) 129 #define H_BK_VE_DISC(x) BK_REG_H(REG_BASE_VE_DISC, x) 130 131 #define REG_IPMUX_02_L (REG_IPMUX_BASE + 0x04) 132 133 /* LPLL */ 134 #define L_BK_LPLL(x) BK_REG_L(REG_LPLL_BASE, x) 135 #define H_BK_LPLL(x) BK_REG_H(REG_LPLL_BASE, x) 136 137 /* Chip Top */ 138 #define L_BK_CHIPTOP(x) BK_REG_L(REG_CHIPTOP_BASE, x) 139 #define H_BK_CHIPTOP(x) BK_REG_H(REG_CHIPTOP_BASE, x) 140 141 /* Chip Top */ 142 #define L_BK_CHIP(x) BK_REG_L(REG_BASE_CHIP, x) 143 #define H_BK_CHIP(x) BK_REG_H(REG_BASE_CHIP, x) 144 145 /* CLKGEN0 */ 146 #define L_BK_CLKGEN0(x) BK_REG_L(REG_CLKGEN0_BASE, x) 147 #define H_BK_CLKGEN0(x) BK_REG_H(REG_CLKGEN0_BASE, x) 148 149 /* PM_SLP */ 150 #define L_BK_PMSLP(x) BK_REG_L(REG_BASE_PM_SLP, x) 151 #define H_BK_PMSLP(x) BK_REG_H(REG_BASE_PM_SLP, x) 152 153 /* OTP */ 154 #define L_BK_PMOTP(x) BK_REG_L(REG_BASE_PM_OTP, x) 155 #define H_BK_PMOTP(x) BK_REG_H(REG_BASE_PM_OTP, x) 156 157 #define REG_SC_BK02_2C_L (REG_SC_BASE + 0x0200 + 0x58) 158 #define REG_SC_BK20_03_L (REG_SC_BASE + 0x2000 + 0x06) 159 #define REG_SC_BK57_2F_L (REG_SC_BASE + 0x5700 + 0x5E) 160 #define REG_SC_BK57_7E_L (REG_SC_BASE + 0x5700 + 0xFC) 161 #define REG_SC_BK57_7F_L (REG_SC_BASE + 0x5700 + 0xFE) 162 163 //------------------------------------------------------------------------------ 164 // Input source select 165 166 // BK_IP1F2_02 [2:0] 167 #define IP_INSSEL_ANALOG1 0x0000 168 #define IP_INSSEL_ANALOG2 0x0001 169 #define IP_INSSEL_ANALOG3 0x0002 170 #define IP_INSSEL_DVI 0x0003 171 #define IP_INSSEL_VIDEO 0x0004 172 #define IP_INSSEL_HDTV 0x0005 173 #define IP_INSSEL_HDMI 0x0007 174 175 #define IP_INSSEL_MASK BITMASK(2:0) 176 #define IP_VDOSEL_MASK BITMASK(1:0) 177 178 typedef enum 179 { 180 IP_CCIR656_A, 181 IP_MST_VD_A, 182 IP_CCIR601, 183 IP_MST_VD_B, // Don't use; RD's suggestion. 184 IP_CCIR656_B=0x20 185 } VDOSEL; 186 187 188 typedef enum 189 { 190 VE_IPMUX_ADC_A = 0, ///< ADC A 191 VE_IPMUX_HDMI_DVI = 1, ///< DVI 192 VE_IPMUX_VD = 2, ///< VD 193 VE_IPMUX_MVOP = 3, ///< MPEG/DC0 194 VE_IPMUX_SC_IP1 = 4, ///< Scaler IP1 output 195 VE_IPMUX_EXT_VD = 5, ///< External VD 196 VE_IPMUX_ADC_B = 6, ///< ADC B 197 VE_IPMUX_CAPTURE = 7, ///< Scaler OP2 output 198 VE_IPMUX_MVOP2 = 8, ///< DC1 199 VE_IPMUX_SC_SUBIP = 9, ///< SUB IP 200 VE_IPMUX_DI = 10, ///< after DI 201 } VE_IPMUX_TYPE; 202 203 typedef enum 204 { 205 AUTO_DETECT =0x00, 206 HV_SEPARATED =0x01, 207 COMPOSITE_SYNC =0x02, 208 SYNC_ON_GREEN =0x03 209 }STYPE; 210 211 typedef enum 212 { 213 CSYNC = 0, 214 SOG = 1 215 }COMP; 216 217 //------------------------------------------------------------------------------ 218 // ADC 219 220 #define ADC_AMUXA_MASK BITMASK(1:0) 221 #define ADC_YMUX_MASK BITMASK(3:0) 222 #define ADC_CMUX_MASK BITMASK(7:4) 223 224 225 //------------------------------------------------------------------------------ 226 // MUX 227 228 typedef enum 229 { 230 ADC_RGB1, 231 ADC_RGB2, 232 ADC_RGB3, 233 }AMUX_SEL; 234 235 typedef enum // For PC/YPbPr input mux 236 { 237 ANALOG_RGB0 = ADC_RGB1, 238 ANALOG_RGB1 = ADC_RGB2, 239 ANALOG_RGB2 = ADC_RGB3, 240 ANALOG_RGB_DUMMY, 241 }ANALOG_RGB; 242 243 typedef enum 244 { 245 MSVD_YMUX_CVBS0, 246 MSVD_YMUX_CVBS1, 247 MSVD_YMUX_CVBS2, 248 MSVD_YMUX_CVBS3, 249 250 MSVD_YMUX_Y0, 251 MSVD_YMUX_Y1, 252 MSVD_YMUX_C0, 253 MSVD_YMUX_C1, 254 255 MSVD_YMUX_SOG0 = 8, 256 MSVD_YMUX_SOG1, 257 MSVD_YMUX_SOG2, 258 259 MSVD_YMUX_G0 = 11, 260 MSVD_YMUX_G1 = 12, 261 MSVD_YMUX_G2 = 13, 262 MSVD_YMUX_CVBS4 = MSVD_YMUX_Y0, 263 MSVD_YMUX_CVBS5 = MSVD_YMUX_Y1, 264 MSVD_YMUX_CVBS6 = MSVD_YMUX_C0, 265 MSVD_YMUX_CVBS7 = MSVD_YMUX_C1, 266 MSVD_YMUX_NONE = 0xF, 267 268 MSVD_YMUX_DUMMY, 269 }MS_VD_YMUX; 270 271 typedef enum 272 { 273 MSVD_CMUX_CVBS0, 274 MSVD_CMUX_CVBS1, 275 MSVD_CMUX_CVBS2, 276 MSVD_CMUX_CVBS3, 277 278 MSVD_CMUX_Y0 = 4, 279 MSVD_CMUX_Y1, 280 MSVD_CMUX_C0, 281 MSVD_CMUX_C1, 282 283 MSVD_CMUX_SOG0 = 8, 284 MSVD_CMUX_SOG1, 285 MSVD_CMUX_SOG2, 286 287 MSVD_CMUX_R0 = 11, 288 MSVD_CMUX_R1 = 12, 289 MSVD_CMUX_R2 = 13, 290 MSVD_CMUX_CVBS4 = MSVD_CMUX_Y0, 291 MSVD_CMUX_CVBS5 = MSVD_CMUX_C0, 292 MSVD_CMUX_CVBS6 = MSVD_CMUX_Y1, 293 MSVD_CMUX_CVBS7 = MSVD_CMUX_C1, 294 MSVD_CMUX_NONE = 0xF, 295 296 MSVD_CMUX_DUMMY, 297 }MS_VD_CMUX; 298 299 //------------------------------------------------------------------------------ 300 // SCART 301 302 typedef enum // For specify scart RGB input 303 { 304 SCART_RGB0 = 0x00, 305 SCART_RGB1, 306 SCART_RGB2, 307 SCART_RGB_DUMMY, 308 }SCART_RGB; 309 310 typedef enum // 0x2580[5:4] 311 { 312 SCART_FB_NONE = 0x00, 313 SCART_FB0, 314 SCART_FB1, 315 SCART_FB2, 316 }SCART_FB; 317 318 #define SCART_RGB_NONE 0xFF 319 320 321 // CEC porting 322 #ifdef SATURN_IV_ENHANCE 323 #define L_BK_CEC(x) BK_REG_L(CEC_REG_BASE, x) 324 #define H_BK_CEC(x) BK_REG_H(CEC_REG_BASE, x) 325 #endif 326 327 /////////////////////////////////////////////////////// 328 // MDHI bank 329 /////////////////////////////////////////////////////// 330 331 #define L(x) ((x) + 0) 332 #define H(x) ((x) + 1) 333 #define __REG_HDMI(idx) (REG_HDMI_BASE + (idx) * 2) 334 335 #define REG_HDMI_SYSCONFIG __REG_HDMI(0x00) 336 #define REG_HDMI_ST1 __REG_HDMI(0x01) 337 #define REG_HDMI_ST2 __REG_HDMI(0x02) 338 #define REG_HDMI_ERR1 __REG_HDMI(0x04) 339 #define REG_HDMI_CONFIG1 __REG_HDMI(0x06) 340 #define REG_HDMI_CONFIG2 __REG_HDMI(0x07) 341 #define REG_HDMI_CONFIG3 __REG_HDMI(0x08) 342 #define REG_HDMI_CONFIG4 __REG_HDMI(0x09) 343 #define REG_HDMI_CLK_CFG __REG_HDMI(0x0A) 344 #define REG_HDMI_TMCTRL __REG_HDMI(0x0B) 345 #define REG_HDMI_FREQ_CMPVAL1 __REG_HDMI(0x0C) 346 #define REG_HDMI_FREQ_CMPVAL2 __REG_HDMI(0x0D) 347 #define REG_HDMI_FREQ_CMPVAL3 __REG_HDMI(0x0E) 348 #define REG_HDMI_PKT_TYPE __REG_HDMI(0x10) 349 #define REG_HDMI_PCLK_FREQ __REG_HDMI(0x11) 350 #define REG_HDMI_AUDIO_CLK0 __REG_HDMI(0x12) 351 #define REG_HDMI_AUDIO_CLK1 __REG_HDMI(0x13) 352 #define REG_HDMI_AUDIO_CLK2 __REG_HDMI(0x14) 353 #define REG_HDMI_GCONTROL __REG_HDMI(0x15) 354 #define REG_HDMI_ACP_HB1 __REG_HDMI(0x16) 355 #define REG_HDMI_ACP_DATA0 __REG_HDMI(0x17) 356 #define REG_HDMI_ACP_DATA1 __REG_HDMI(0x18) 357 #define REG_HDMI_ACP_DATA2 __REG_HDMI(0x19) 358 #define REG_HDMI_ACP_DATA3 __REG_HDMI(0x1A) 359 #define REG_HDMI_ACP_DATA4 __REG_HDMI(0x1B) 360 #define REG_HDMI_ACP_DATA5 __REG_HDMI(0x1C) 361 #define REG_HDMI_ACP_DATA6 __REG_HDMI(0x1D) 362 #define REG_HDMI_ACP_DATA7 __REG_HDMI(0x1E) 363 #define REG_HDMI_ISRC_HB1 __REG_HDMI(0x1F) 364 #define REG_HDMI_ISRC_DATA0 __REG_HDMI(0x20) 365 #define REG_HDMI_ISRC_DATA1 __REG_HDMI(0x21) 366 #define REG_HDMI_ISRC_DATA2 __REG_HDMI(0x22) 367 #define REG_HDMI_ISRC_DATA3 __REG_HDMI(0x23) 368 #define REG_HDMI_ISRC_DATA4 __REG_HDMI(0x24) 369 #define REG_HDMI_ISRC_DATA5 __REG_HDMI(0x25) 370 #define REG_HDMI_ISRC_DATA6 __REG_HDMI(0x26) 371 #define REG_HDMI_ISRC_DATA7 __REG_HDMI(0x27) 372 #define REG_HDMI_ISRC_DATA8 __REG_HDMI(0x28) 373 #define REG_HDMI_ISRC_DATA9 __REG_HDMI(0x29) 374 #define REG_HDMI_ISRC_DATA10 __REG_HDMI(0x2A) 375 #define REG_HDMI_ISRC_DATA11 __REG_HDMI(0x2B) 376 #define REG_HDMI_ISRC_DATA12 __REG_HDMI(0x2C) 377 #define REG_HDMI_ISRC_DATA13 __REG_HDMI(0x2D) 378 #define REG_HDMI_ISRC_DATA14 __REG_HDMI(0x2E) 379 #define REG_HDMI_ISRC_DATA15 __REG_HDMI(0x2F) 380 #define REG_HDMI_VS_HDR0 __REG_HDMI(0x30) 381 #define REG_HDMI_VS_HDR1 __REG_HDMI(0x31) 382 #define REG_HDMI_VS_IF0 __REG_HDMI(0x32) 383 #define REG_HDMI_VS_IF1 __REG_HDMI(0x33) 384 #define REG_HDMI_VS_IF2 __REG_HDMI(0x34) 385 #define REG_HDMI_VS_IF3 __REG_HDMI(0x35) 386 #define REG_HDMI_VS_IF4 __REG_HDMI(0x36) 387 #define REG_HDMI_VS_IF5 __REG_HDMI(0x37) 388 #define REG_HDMI_VS_IF6 __REG_HDMI(0x38) 389 #define REG_HDMI_VS_IF7 __REG_HDMI(0x39) 390 #define REG_HDMI_VS_IF8 __REG_HDMI(0x3A) 391 #define REG_HDMI_VS_IF9 __REG_HDMI(0x3B) 392 #define REG_HDMI_VS_IF10 __REG_HDMI(0x3C) 393 #define REG_HDMI_VS_IF11 __REG_HDMI(0x3D) 394 #define REG_HDMI_VS_IF12 __REG_HDMI(0x3E) 395 #define REG_HDMI_VS_IF13 __REG_HDMI(0x3F) 396 #define REG_HDMI_AVI_IF0 __REG_HDMI(0x40) 397 #define REG_HDMI_AVI_IF1 __REG_HDMI(0x41) 398 #define REG_HDMI_AVI_IF2 __REG_HDMI(0x42) 399 #define REG_HDMI_AVI_IF3 __REG_HDMI(0x43) 400 #define REG_HDMI_AVI_IF4 __REG_HDMI(0x44) 401 #define REG_HDMI_AVI_IF5 __REG_HDMI(0x45) 402 #define REG_HDMI_AVI_IF6 __REG_HDMI(0x46) 403 #define REG_HDMI_SPD_IF0 __REG_HDMI(0x47) 404 #define REG_HDMI_SPD_IF1 __REG_HDMI(0x48) 405 #define REG_HDMI_SPD_IF2 __REG_HDMI(0x49) 406 #define REG_HDMI_SPD_IF3 __REG_HDMI(0x4A) 407 #define REG_HDMI_SPD_IF4 __REG_HDMI(0x4B) 408 #define REG_HDMI_SPD_IF5 __REG_HDMI(0x4C) 409 #define REG_HDMI_SPD_IF6 __REG_HDMI(0x4D) 410 #define REG_HDMI_SPD_IF7 __REG_HDMI(0x4E) 411 #define REG_HDMI_SPD_IF8 __REG_HDMI(0x4F) 412 #define REG_HDMI_SPD_IF9 __REG_HDMI(0x50) 413 #define REG_HDMI_SPD_IF10 __REG_HDMI(0x51) 414 #define REG_HDMI_SPD_IF11 __REG_HDMI(0x52) 415 #define REG_HDMI_SPD_IF12 __REG_HDMI(0x53) 416 #define REG_HDMI_AUDIO_IF0 __REG_HDMI(0x54) 417 #define REG_HDMI_AUDIO_IF1 __REG_HDMI(0x55) 418 #define REG_HDMI_AUDIO_IF2 __REG_HDMI(0x56) 419 #define REG_HDMI_MPEG_IF0 __REG_HDMI(0x57) 420 #define REG_HDMI_MPEG_IF1 __REG_HDMI(0x58) 421 #define REG_HDMI_MPEG_IF2 __REG_HDMI(0x59) 422 #define REG_HDMI_CS0 __REG_HDMI(0x5A) 423 #define REG_HDMI_CS1 __REG_HDMI(0x5B) 424 #define REG_HDMI_CS2 __REG_HDMI(0x5C) 425 #define REG_HDMI_PLL_CTRL1 __REG_HDMI(0x5D) 426 #define REG_HDMI_PLL_CTRL2 __REG_HDMI(0x5E) 427 #define REG_HDMI_PLL_CTRL3 __REG_HDMI(0x5F) 428 #define REG_HDMI_INT_MASK __REG_HDMI(0x60) 429 #define REG_HDMI_INT_STATUS __REG_HDMI(0x61) 430 #define REG_HDMI_INT_FORCE __REG_HDMI(0x62) 431 #define REG_HDMI_INT_CLEAR __REG_HDMI(0x63) 432 #define REG_HDMI_RESET_PACKET __REG_HDMI(0x64) 433 #define REG_HDMI_AUTO_MODE __REG_HDMI(0x65) 434 #define REG_HDMI_FRAME_RP_VAL __REG_HDMI(0x66) 435 #define REG_HDMI_CEC_CONFIG1 __REG_HDMI(0x67) 436 #define REG_HDMI_CEC_CONFIG2 __REG_HDMI(0x68) 437 #define REG_HDMI_CEC_CONFIG3 __REG_HDMI(0x69) 438 #define REG_HDMI_CEC_CONFIG4 __REG_HDMI(0x6A) 439 #define REG_HDMI_CEC_STATUS1 __REG_HDMI(0x6C) 440 #define REG_HDMI_CEC_TX_DATA0 __REG_HDMI(0x70) 441 #define REG_HDMI_CEC_TX_DATA1 __REG_HDMI(0x71) 442 #define REG_HDMI_CEC_RX_DATA0 __REG_HDMI(0x78) 443 #define REG_HDMI_CEC_RX_DATA1 __REG_HDMI(0x79) 444 445 446 #define __REG_HDCP(idx) (REG_HDCP_BASE + (idx) * 2) 447 448 #define REG_HDCP_00 __REG_HDCP(0x00) 449 #define REG_HDCP_STATUS __REG_HDCP(0x01) 450 #define REG_HDCP_02 __REG_HDCP(0x02) 451 #define REG_HDCP_03 __REG_HDCP(0x03) 452 453 #define REG_BANK_MACE 0x05 454 #define REG_BANK_COMB 0x06 // VD Comb bank 455 456 //------------------------------------------------------------------------------ 457 // HDMI 458 459 #define MS_HDMI_ACP_PKT BIT11 460 #define MS_HDMI_ISRC1_PKT BIT10 461 #define MS_HDMI_ISRC2_PKT BIT9 462 #define MS_HDMI_NULL_PKT BIT8 463 #define MS_HDMI_VS_PKT BIT7 464 #define MS_HDMI_ACR_PKT BIT6 465 #define MS_HDMI_ASAMPLE_PKT BIT5 466 #define MS_HDMI_GC_PKT BIT4 467 #define MS_HDMI_AVI_PKT BIT3 468 #define MS_HDMI_SPD_PKT BIT2 469 #define MS_HDMI_AUI_PKT BIT1 470 #define MS_HDMI_MPEG_PKT BIT0 471 472 //------------------------------------------------------------------------------ 473 // DVI 474 475 typedef enum 476 { 477 DVI_SW_A, 478 DVI_SW_B, 479 }DVI_CH_SEL; 480 481 482 /////////////////////////////////////////////////////// 483 // AFEC bank 484 /////////////////////////////////////////////////////// 485 486 #define BK_AFEC_01 (AFEC_REG_BASE+0x01) 487 #define BK_AFEC_02 (AFEC_REG_BASE+0x02) 488 #define BK_AFEC_03 (AFEC_REG_BASE+0x03) 489 #define BK_AFEC_04 (AFEC_REG_BASE+0x04) 490 #define BK_AFEC_05 (AFEC_REG_BASE+0x05) 491 #define BK_AFEC_06 (AFEC_REG_BASE+0x06) 492 #define BK_AFEC_07 (AFEC_REG_BASE+0x07) 493 #define BK_AFEC_08 (AFEC_REG_BASE+0x08) 494 #define BK_AFEC_09 (AFEC_REG_BASE+0x09) 495 #define BK_AFEC_0A (AFEC_REG_BASE+0x0A) 496 #define BK_AFEC_0B (AFEC_REG_BASE+0x0B) 497 #define BK_AFEC_0C (AFEC_REG_BASE+0x0C) 498 #define BK_AFEC_0D (AFEC_REG_BASE+0x0D) 499 #define BK_AFEC_0E (AFEC_REG_BASE+0x0E) 500 #define BK_AFEC_0F (AFEC_REG_BASE+0x0F) 501 #define BK_AFEC_10 (AFEC_REG_BASE+0x10) 502 #define BK_AFEC_11 (AFEC_REG_BASE+0x11) 503 #define BK_AFEC_12 (AFEC_REG_BASE+0x12) 504 #define BK_AFEC_13 (AFEC_REG_BASE+0x13) 505 #define BK_AFEC_14 (AFEC_REG_BASE+0x14) 506 #define BK_AFEC_15 (AFEC_REG_BASE+0x15) 507 #define BK_AFEC_16 (AFEC_REG_BASE+0x16) 508 #define BK_AFEC_17 (AFEC_REG_BASE+0x17) 509 #define BK_AFEC_18 (AFEC_REG_BASE+0x18) 510 #define BK_AFEC_19 (AFEC_REG_BASE+0x19) 511 #define BK_AFEC_1A (AFEC_REG_BASE+0x1A) 512 #define BK_AFEC_1B (AFEC_REG_BASE+0x1B) 513 #define BK_AFEC_1C (AFEC_REG_BASE+0x1C) 514 #define BK_AFEC_1D (AFEC_REG_BASE+0x1D) 515 #define BK_AFEC_1E (AFEC_REG_BASE+0x1E) 516 #define BK_AFEC_1F (AFEC_REG_BASE+0x1F) 517 #define BK_AFEC_20 (AFEC_REG_BASE+0x20) 518 #define BK_AFEC_21 (AFEC_REG_BASE+0x21) 519 #define BK_AFEC_22 (AFEC_REG_BASE+0x22) 520 #define BK_AFEC_23 (AFEC_REG_BASE+0x23) 521 #define BK_AFEC_24 (AFEC_REG_BASE+0x24) 522 #define BK_AFEC_25 (AFEC_REG_BASE+0x25) 523 #define BK_AFEC_26 (AFEC_REG_BASE+0x26) 524 #define BK_AFEC_27 (AFEC_REG_BASE+0x27) 525 #define BK_AFEC_28 (AFEC_REG_BASE+0x28) 526 #define BK_AFEC_29 (AFEC_REG_BASE+0x29) 527 #define BK_AFEC_2A (AFEC_REG_BASE+0x2A) 528 #define BK_AFEC_2B (AFEC_REG_BASE+0x2B) 529 #define BK_AFEC_2C (AFEC_REG_BASE+0x2C) 530 #define BK_AFEC_2D (AFEC_REG_BASE+0x2D) 531 #define BK_AFEC_2E (AFEC_REG_BASE+0x2E) 532 #define BK_AFEC_2F (AFEC_REG_BASE+0x2F) 533 #define BK_AFEC_30 (AFEC_REG_BASE+0x30) 534 #define BK_AFEC_31 (AFEC_REG_BASE+0x31) 535 #define BK_AFEC_32 (AFEC_REG_BASE+0x32) 536 #define BK_AFEC_33 (AFEC_REG_BASE+0x33) 537 #define BK_AFEC_34 (AFEC_REG_BASE+0x34) 538 #define BK_AFEC_35 (AFEC_REG_BASE+0x35) 539 #define BK_AFEC_36 (AFEC_REG_BASE+0x36) 540 #define BK_AFEC_37 (AFEC_REG_BASE+0x37) 541 #define BK_AFEC_38 (AFEC_REG_BASE+0x38) 542 #define BK_AFEC_39 (AFEC_REG_BASE+0x39) 543 #define BK_AFEC_3A (AFEC_REG_BASE+0x3A) 544 #define BK_AFEC_3B (AFEC_REG_BASE+0x3B) 545 #define BK_AFEC_3C (AFEC_REG_BASE+0x3C) 546 #define BK_AFEC_3D (AFEC_REG_BASE+0x3D) 547 #define BK_AFEC_3E (AFEC_REG_BASE+0x3E) 548 #define BK_AFEC_3F (AFEC_REG_BASE+0x3F) 549 #define BK_AFEC_40 (AFEC_REG_BASE+0x40) 550 #define BK_AFEC_41 (AFEC_REG_BASE+0x41) 551 #define BK_AFEC_42 (AFEC_REG_BASE+0x42) 552 #define BK_AFEC_43 (AFEC_REG_BASE+0x43) 553 #define BK_AFEC_44 (AFEC_REG_BASE+0x44) 554 #define BK_AFEC_45 (AFEC_REG_BASE+0x45) 555 #define BK_AFEC_46 (AFEC_REG_BASE+0x46) 556 #define BK_AFEC_47 (AFEC_REG_BASE+0x47) 557 #define BK_AFEC_48 (AFEC_REG_BASE+0x48) 558 #define BK_AFEC_49 (AFEC_REG_BASE+0x49) 559 #define BK_AFEC_4A (AFEC_REG_BASE+0x4A) 560 #define BK_AFEC_4B (AFEC_REG_BASE+0x4B) 561 #define BK_AFEC_4C (AFEC_REG_BASE+0x4C) 562 #define BK_AFEC_4D (AFEC_REG_BASE+0x4D) 563 #define BK_AFEC_4E (AFEC_REG_BASE+0x4E) 564 #define BK_AFEC_4F (AFEC_REG_BASE+0x4F) 565 #define BK_AFEC_50 (AFEC_REG_BASE+0x50) 566 #define BK_AFEC_51 (AFEC_REG_BASE+0x51) 567 #define BK_AFEC_52 (AFEC_REG_BASE+0x52) 568 #define BK_AFEC_53 (AFEC_REG_BASE+0x53) 569 #define BK_AFEC_54 (AFEC_REG_BASE+0x54) 570 #define BK_AFEC_55 (AFEC_REG_BASE+0x55) 571 #define BK_AFEC_56 (AFEC_REG_BASE+0x56) 572 #define BK_AFEC_57 (AFEC_REG_BASE+0x57) 573 #define BK_AFEC_58 (AFEC_REG_BASE+0x58) 574 #define BK_AFEC_59 (AFEC_REG_BASE+0x59) 575 #define BK_AFEC_5A (AFEC_REG_BASE+0x5A) 576 #define BK_AFEC_5B (AFEC_REG_BASE+0x5B) 577 #define BK_AFEC_5C (AFEC_REG_BASE+0x5C) 578 #define BK_AFEC_5D (AFEC_REG_BASE+0x5D) 579 #define BK_AFEC_5E (AFEC_REG_BASE+0x5E) 580 #define BK_AFEC_5F (AFEC_REG_BASE+0x5F) 581 #define BK_AFEC_60 (AFEC_REG_BASE+0x60) 582 #define BK_AFEC_61 (AFEC_REG_BASE+0x61) 583 #define BK_AFEC_62 (AFEC_REG_BASE+0x62) 584 #define BK_AFEC_63 (AFEC_REG_BASE+0x63) 585 #define BK_AFEC_64 (AFEC_REG_BASE+0x64) 586 #define BK_AFEC_65 (AFEC_REG_BASE+0x65) 587 #define BK_AFEC_66 (AFEC_REG_BASE+0x66) 588 #define BK_AFEC_67 (AFEC_REG_BASE+0x67) 589 #define BK_AFEC_68 (AFEC_REG_BASE+0x68) 590 #define BK_AFEC_69 (AFEC_REG_BASE+0x69) 591 #define BK_AFEC_6A (AFEC_REG_BASE+0x6A) 592 #define BK_AFEC_6B (AFEC_REG_BASE+0x6B) 593 #define BK_AFEC_6C (AFEC_REG_BASE+0x6C) 594 #define BK_AFEC_6D (AFEC_REG_BASE+0x6D) 595 #define BK_AFEC_6E (AFEC_REG_BASE+0x6E) 596 #define BK_AFEC_6F (AFEC_REG_BASE+0x6F) 597 #define BK_AFEC_70 (AFEC_REG_BASE+0x70) 598 #define BK_AFEC_71 (AFEC_REG_BASE+0x71) 599 #define BK_AFEC_72 (AFEC_REG_BASE+0x72) 600 #define BK_AFEC_73 (AFEC_REG_BASE+0x73) 601 #define BK_AFEC_74 (AFEC_REG_BASE+0x74) 602 #define BK_AFEC_75 (AFEC_REG_BASE+0x75) 603 #define BK_AFEC_76 (AFEC_REG_BASE+0x76) 604 #define BK_AFEC_77 (AFEC_REG_BASE+0x77) 605 #define BK_AFEC_78 (AFEC_REG_BASE+0x78) 606 #define BK_AFEC_79 (AFEC_REG_BASE+0x79) 607 #define BK_AFEC_7A (AFEC_REG_BASE+0x7A) 608 #define BK_AFEC_7B (AFEC_REG_BASE+0x7B) 609 #define BK_AFEC_7C (AFEC_REG_BASE+0x7C) 610 #define BK_AFEC_7D (AFEC_REG_BASE+0x7D) 611 #define BK_AFEC_7E (AFEC_REG_BASE+0x7E) 612 #define BK_AFEC_7F (AFEC_REG_BASE+0x7F) 613 #define BK_AFEC_80 (AFEC_REG_BASE+0x80) 614 #define BK_AFEC_81 (AFEC_REG_BASE+0x81) 615 #define BK_AFEC_82 (AFEC_REG_BASE+0x82) 616 #define BK_AFEC_83 (AFEC_REG_BASE+0x83) 617 #define BK_AFEC_84 (AFEC_REG_BASE+0x84) 618 #define BK_AFEC_85 (AFEC_REG_BASE+0x85) 619 #define BK_AFEC_86 (AFEC_REG_BASE+0x86) 620 #define BK_AFEC_87 (AFEC_REG_BASE+0x87) 621 #define BK_AFEC_88 (AFEC_REG_BASE+0x88) 622 #define BK_AFEC_89 (AFEC_REG_BASE+0x89) 623 #define BK_AFEC_8A (AFEC_REG_BASE+0x8A) 624 #define BK_AFEC_8B (AFEC_REG_BASE+0x8B) 625 #define BK_AFEC_8C (AFEC_REG_BASE+0x8C) 626 #define BK_AFEC_8D (AFEC_REG_BASE+0x8D) 627 #define BK_AFEC_8E (AFEC_REG_BASE+0x8E) 628 #define BK_AFEC_8F (AFEC_REG_BASE+0x8F) 629 #define BK_AFEC_90 (AFEC_REG_BASE+0x90) 630 #define BK_AFEC_91 (AFEC_REG_BASE+0x91) 631 #define BK_AFEC_92 (AFEC_REG_BASE+0x92) 632 #define BK_AFEC_93 (AFEC_REG_BASE+0x93) 633 #define BK_AFEC_94 (AFEC_REG_BASE+0x94) 634 #define BK_AFEC_95 (AFEC_REG_BASE+0x95) 635 #define BK_AFEC_96 (AFEC_REG_BASE+0x96) 636 #define BK_AFEC_97 (AFEC_REG_BASE+0x97) 637 #define BK_AFEC_98 (AFEC_REG_BASE+0x98) 638 #define BK_AFEC_99 (AFEC_REG_BASE+0x99) 639 #define BK_AFEC_9A (AFEC_REG_BASE+0x9A) 640 #define BK_AFEC_9B (AFEC_REG_BASE+0x9B) 641 #define BK_AFEC_9C (AFEC_REG_BASE+0x9C) 642 #define BK_AFEC_9D (AFEC_REG_BASE+0x9D) 643 #define BK_AFEC_9E (AFEC_REG_BASE+0x9E) 644 #define BK_AFEC_9F (AFEC_REG_BASE+0x9F) 645 #define BK_AFEC_A0 (AFEC_REG_BASE+0xA0) 646 #define BK_AFEC_A1 (AFEC_REG_BASE+0xA1) 647 #define BK_AFEC_A2 (AFEC_REG_BASE+0xA2) 648 #define BK_AFEC_A3 (AFEC_REG_BASE+0xA3) 649 #define BK_AFEC_A4 (AFEC_REG_BASE+0xA4) 650 #define BK_AFEC_A5 (AFEC_REG_BASE+0xA5) 651 #define BK_AFEC_A6 (AFEC_REG_BASE+0xA6) 652 #define BK_AFEC_A7 (AFEC_REG_BASE+0xA7) 653 #define BK_AFEC_A8 (AFEC_REG_BASE+0xA8) 654 #define BK_AFEC_A9 (AFEC_REG_BASE+0xA9) 655 #define BK_AFEC_AA (AFEC_REG_BASE+0xAA) 656 #define BK_AFEC_AB (AFEC_REG_BASE+0xAB) 657 #define BK_AFEC_AC (AFEC_REG_BASE+0xAC) 658 #define BK_AFEC_AD (AFEC_REG_BASE+0xAD) 659 #define BK_AFEC_AE (AFEC_REG_BASE+0xAE) 660 #define BK_AFEC_AF (AFEC_REG_BASE+0xAF) 661 #define BK_AFEC_B0 (AFEC_REG_BASE+0xB0) 662 #define BK_AFEC_B1 (AFEC_REG_BASE+0xB1) 663 #define BK_AFEC_B2 (AFEC_REG_BASE+0xB2) 664 #define BK_AFEC_B3 (AFEC_REG_BASE+0xB3) 665 #define BK_AFEC_B4 (AFEC_REG_BASE+0xB4) 666 #define BK_AFEC_B5 (AFEC_REG_BASE+0xB5) 667 #define BK_AFEC_B6 (AFEC_REG_BASE+0xB6) 668 #define BK_AFEC_B7 (AFEC_REG_BASE+0xB7) 669 #define BK_AFEC_B8 (AFEC_REG_BASE+0xB8) 670 #define BK_AFEC_B9 (AFEC_REG_BASE+0xB9) 671 #define BK_AFEC_BA (AFEC_REG_BASE+0xBA) 672 #define BK_AFEC_BB (AFEC_REG_BASE+0xBB) 673 #define BK_AFEC_BC (AFEC_REG_BASE+0xBC) 674 #define BK_AFEC_BD (AFEC_REG_BASE+0xBD) 675 #define BK_AFEC_BE (AFEC_REG_BASE+0xBE) 676 #define BK_AFEC_BF (AFEC_REG_BASE+0xBF) 677 #define BK_AFEC_C0 (AFEC_REG_BASE+0xC0) 678 #define BK_AFEC_C1 (AFEC_REG_BASE+0xC1) 679 #define BK_AFEC_C2 (AFEC_REG_BASE+0xC2) 680 #define BK_AFEC_C3 (AFEC_REG_BASE+0xC3) 681 #define BK_AFEC_C4 (AFEC_REG_BASE+0xC4) 682 #define BK_AFEC_C5 (AFEC_REG_BASE+0xC5) 683 #define BK_AFEC_C6 (AFEC_REG_BASE+0xC6) 684 #define BK_AFEC_C7 (AFEC_REG_BASE+0xC7) 685 #define BK_AFEC_C8 (AFEC_REG_BASE+0xC8) 686 #define BK_AFEC_C9 (AFEC_REG_BASE+0xC9) 687 #define BK_AFEC_CA (AFEC_REG_BASE+0xCA) 688 #define BK_AFEC_CB (AFEC_REG_BASE+0xCB) 689 #define BK_AFEC_CC (AFEC_REG_BASE+0xCC) 690 #define BK_AFEC_CD (AFEC_REG_BASE+0xCD) 691 #define BK_AFEC_CE (AFEC_REG_BASE+0xCE) 692 #define BK_AFEC_CF (AFEC_REG_BASE+0xCF) 693 #define BK_AFEC_D0 (AFEC_REG_BASE+0xD0) 694 #define BK_AFEC_D1 (AFEC_REG_BASE+0xD1) 695 #define BK_AFEC_D2 (AFEC_REG_BASE+0xD2) 696 #define BK_AFEC_D3 (AFEC_REG_BASE+0xD3) 697 #define BK_AFEC_D4 (AFEC_REG_BASE+0xD4) 698 #define BK_AFEC_D5 (AFEC_REG_BASE+0xD5) 699 #define BK_AFEC_D6 (AFEC_REG_BASE+0xD6) 700 #define BK_AFEC_D7 (AFEC_REG_BASE+0xD7) 701 #define BK_AFEC_D8 (AFEC_REG_BASE+0xD8) 702 #define BK_AFEC_D9 (AFEC_REG_BASE+0xD9) 703 #define BK_AFEC_DA (AFEC_REG_BASE+0xDA) 704 #define BK_AFEC_DB (AFEC_REG_BASE+0xDB) 705 #define BK_AFEC_DC (AFEC_REG_BASE+0xDC) 706 #define BK_AFEC_DD (AFEC_REG_BASE+0xDD) 707 #define BK_AFEC_DE (AFEC_REG_BASE+0xDE) 708 #define BK_AFEC_DF (AFEC_REG_BASE+0xDF) 709 #define BK_AFEC_E0 (AFEC_REG_BASE+0xE0) 710 #define BK_AFEC_E1 (AFEC_REG_BASE+0xE1) 711 #define BK_AFEC_E2 (AFEC_REG_BASE+0xE2) 712 #define BK_AFEC_E3 (AFEC_REG_BASE+0xE3) 713 #define BK_AFEC_E4 (AFEC_REG_BASE+0xE4) 714 #define BK_AFEC_E5 (AFEC_REG_BASE+0xE5) 715 #define BK_AFEC_E6 (AFEC_REG_BASE+0xE6) 716 #define BK_AFEC_E7 (AFEC_REG_BASE+0xE7) 717 #define BK_AFEC_E8 (AFEC_REG_BASE+0xE8) 718 #define BK_AFEC_E9 (AFEC_REG_BASE+0xE9) 719 #define BK_AFEC_EA (AFEC_REG_BASE+0xEA) 720 #define BK_AFEC_EB (AFEC_REG_BASE+0xEB) 721 #define BK_AFEC_EC (AFEC_REG_BASE+0xEC) 722 #define BK_AFEC_ED (AFEC_REG_BASE+0xED) 723 #define BK_AFEC_EE (AFEC_REG_BASE+0xEE) 724 #define BK_AFEC_EF (AFEC_REG_BASE+0xEF) 725 #define BK_AFEC_F0 (AFEC_REG_BASE+0xF0) 726 #define BK_AFEC_F1 (AFEC_REG_BASE+0xF1) 727 #define BK_AFEC_F2 (AFEC_REG_BASE+0xF2) 728 #define BK_AFEC_F3 (AFEC_REG_BASE+0xF3) 729 #define BK_AFEC_F4 (AFEC_REG_BASE+0xF4) 730 #define BK_AFEC_F5 (AFEC_REG_BASE+0xF5) 731 #define BK_AFEC_F6 (AFEC_REG_BASE+0xF6) 732 #define BK_AFEC_F7 (AFEC_REG_BASE+0xF7) 733 #define BK_AFEC_F8 (AFEC_REG_BASE+0xF8) 734 #define BK_AFEC_F9 (AFEC_REG_BASE+0xF9) 735 #define BK_AFEC_FA (AFEC_REG_BASE+0xFA) 736 #define BK_AFEC_FB (AFEC_REG_BASE+0xFB) 737 #define BK_AFEC_FC (AFEC_REG_BASE+0xFC) 738 #define BK_AFEC_FD (AFEC_REG_BASE+0xFD) 739 #define BK_AFEC_FE (AFEC_REG_BASE+0xFE) 740 #define BK_AFEC_FF (AFEC_REG_BASE+0xFF) 741 742 743 //////////////////////////////////////////////////////////////////////////////// 744 // MACE bank 745 //////////////////////////////////////////////////////////////////////////////// 746 #define BK_MACE_01 0x01 747 #define BK_MACE_02 0x02 748 #define BK_MACE_03 0x03 749 #define BK_MACE_04 0x04 750 #define BK_MACE_05 0x05 751 #define BK_MACE_06 0x06 752 #define BK_MACE_07 0x07 753 #define BK_MACE_08 0x08 754 #define BK_MACE_09 0x09 755 #define BK_MACE_0A 0x0A 756 #define BK_MACE_0B 0x0B 757 #define BK_MACE_0C 0x0C 758 #define BK_MACE_0D 0x0D 759 #define BK_MACE_0E 0x0E 760 #define BK_MACE_0F 0x0F 761 #define BK_MACE_10 0x10 762 #define BK_MACE_11 0x11 763 #define BK_MACE_12 0x12 764 #define BK_MACE_13 0x13 765 #define BK_MACE_14 0x14 766 #define BK_MACE_15 0x15 767 #define BK_MACE_16 0x16 768 #define BK_MACE_17 0x17 769 #define BK_MACE_18 0x18 770 #define BK_MACE_19 0x19 771 #define BK_MACE_1A 0x1A 772 #define BK_MACE_1B 0x1B 773 #define BK_MACE_1C 0x1C 774 #define BK_MACE_1D 0x1D 775 #define BK_MACE_1E 0x1E 776 #define BK_MACE_1F 0x1F 777 #define BK_MACE_20 0x20 778 #define BK_MACE_21 0x21 779 #define BK_MACE_22 0x22 780 #define BK_MACE_23 0x23 781 #define BK_MACE_24 0x24 782 #define BK_MACE_25 0x25 783 #define BK_MACE_26 0x26 784 #define BK_MACE_27 0x27 785 #define BK_MACE_28 0x28 786 #define BK_MACE_29 0x29 787 #define BK_MACE_2A 0x2A 788 #define BK_MACE_2B 0x2B 789 #define BK_MACE_2C 0x2C 790 #define BK_MACE_2D 0x2D 791 #define BK_MACE_2E 0x2E 792 #define BK_MACE_2F 0x2F 793 #define BK_MACE_30 0x30 794 #define BK_MACE_31 0x31 795 #define BK_MACE_32 0x32 796 #define BK_MACE_33 0x33 797 #define BK_MACE_34 0x34 798 #define BK_MACE_35 0x35 799 #define BK_MACE_36 0x36 800 #define BK_MACE_37 0x37 801 #define BK_MACE_38 0x38 802 #define BK_MACE_39 0x39 803 #define BK_MACE_3A 0x3A 804 #define BK_MACE_3B 0x3B 805 #define BK_MACE_3C 0x3C 806 #define BK_MACE_3D 0x3D 807 #define BK_MACE_3E 0x3E 808 #define BK_MACE_3F 0x3F 809 #define BK_MACE_40 0x40 810 #define BK_MACE_41 0x41 811 #define BK_MACE_42 0x42 812 #define BK_MACE_43 0x43 813 #define BK_MACE_44 0x44 814 #define BK_MACE_45 0x45 815 #define BK_MACE_46 0x46 816 #define BK_MACE_47 0x47 817 #define BK_MACE_48 0x48 818 #define BK_MACE_49 0x49 819 #define BK_MACE_4A 0x4A 820 #define BK_MACE_4B 0x4B 821 #define BK_MACE_4C 0x4C 822 #define BK_MACE_4D 0x4D 823 #define BK_MACE_4E 0x4E 824 #define BK_MACE_4F 0x4F 825 #define BK_MACE_50 0x50 826 #define BK_MACE_51 0x51 827 #define BK_MACE_52 0x52 828 #define BK_MACE_53 0x53 829 #define BK_MACE_54 0x54 830 #define BK_MACE_55 0x55 831 #define BK_MACE_56 0x56 832 #define BK_MACE_57 0x57 833 #define BK_MACE_58 0x58 834 #define BK_MACE_59 0x59 835 #define BK_MACE_5A 0x5A 836 #define BK_MACE_5B 0x5B 837 #define BK_MACE_5C 0x5C 838 #define BK_MACE_5D 0x5D 839 #define BK_MACE_5E 0x5E 840 #define BK_MACE_5F 0x5F 841 #define BK_MACE_60 0x60 842 #define BK_MACE_61 0x61 843 #define BK_MACE_62 0x62 844 #define BK_MACE_63 0x63 845 #define BK_MACE_64 0x64 846 #define BK_MACE_65 0x65 847 #define BK_MACE_66 0x66 848 #define BK_MACE_67 0x67 849 #define BK_MACE_68 0x68 850 #define BK_MACE_69 0x69 851 #define BK_MACE_6A 0x6A 852 #define BK_MACE_6B 0x6B 853 #define BK_MACE_6C 0x6C 854 #define BK_MACE_6D 0x6D 855 #define BK_MACE_6E 0x6E 856 #define BK_MACE_6F 0x6F 857 #define BK_MACE_70 0x70 858 #define BK_MACE_71 0x71 859 #define BK_MACE_72 0x72 860 #define BK_MACE_73 0x73 861 #define BK_MACE_74 0x74 862 #define BK_MACE_75 0x75 863 #define BK_MACE_76 0x76 864 #define BK_MACE_77 0x77 865 #define BK_MACE_78 0x78 866 #define BK_MACE_79 0x79 867 #define BK_MACE_7A 0x7A 868 #define BK_MACE_7B 0x7B 869 #define BK_MACE_7C 0x7C 870 #define BK_MACE_7D 0x7D 871 #define BK_MACE_7E 0x7E 872 #define BK_MACE_7F 0x7F 873 #define BK_MACE_80 0x80 874 #define BK_MACE_81 0x81 875 #define BK_MACE_82 0x82 876 #define BK_MACE_83 0x83 877 #define BK_MACE_84 0x84 878 #define BK_MACE_85 0x85 879 #define BK_MACE_86 0x86 880 #define BK_MACE_87 0x87 881 #define BK_MACE_88 0x88 882 #define BK_MACE_89 0x89 883 #define BK_MACE_8A 0x8A 884 #define BK_MACE_8B 0x8B 885 #define BK_MACE_8C 0x8C 886 #define BK_MACE_8D 0x8D 887 #define BK_MACE_8E 0x8E 888 #define BK_MACE_8F 0x8F 889 #define BK_MACE_90 0x90 890 #define BK_MACE_91 0x91 891 #define BK_MACE_92 0x92 892 #define BK_MACE_93 0x93 893 #define BK_MACE_94 0x94 894 #define BK_MACE_95 0x95 895 #define BK_MACE_96 0x96 896 #define BK_MACE_97 0x97 897 #define BK_MACE_98 0x98 898 #define BK_MACE_99 0x99 899 #define BK_MACE_9A 0x9A 900 #define BK_MACE_9B 0x9B 901 #define BK_MACE_9C 0x9C 902 #define BK_MACE_9D 0x9D 903 #define BK_MACE_9E 0x9E 904 #define BK_MACE_9F 0x9F 905 #define BK_MACE_A0 0xA0 906 #define BK_MACE_A1 0xA1 907 #define BK_MACE_A2 0xA2 908 #define BK_MACE_A3 0xA3 909 #define BK_MACE_A4 0xA4 910 #define BK_MACE_A5 0xA5 911 #define BK_MACE_A6 0xA6 912 #define BK_MACE_A7 0xA7 913 #define BK_MACE_A8 0xA8 914 #define BK_MACE_A9 0xA9 915 #define BK_MACE_AA 0xAA 916 #define BK_MACE_AB 0xAB 917 #define BK_MACE_AC 0xAC 918 #define BK_MACE_AD 0xAD 919 #define BK_MACE_AE 0xAE 920 #define BK_MACE_AF 0xAF 921 #define BK_MACE_B0 0xB0 922 #define BK_MACE_B1 0xB1 923 #define BK_MACE_B2 0xB2 924 #define BK_MACE_B3 0xB3 925 #define BK_MACE_B4 0xB4 926 #define BK_MACE_B5 0xB5 927 #define BK_MACE_B6 0xB6 928 #define BK_MACE_B7 0xB7 929 #define BK_MACE_B8 0xB8 930 #define BK_MACE_B9 0xB9 931 #define BK_MACE_BA 0xBA 932 #define BK_MACE_BB 0xBB 933 #define BK_MACE_BC 0xBC 934 #define BK_MACE_BD 0xBD 935 #define BK_MACE_BE 0xBE 936 #define BK_MACE_BF 0xBF 937 #define BK_MACE_C0 0xC0 938 #define BK_MACE_C1 0xC1 939 #define BK_MACE_C2 0xC2 940 #define BK_MACE_C3 0xC3 941 #define BK_MACE_C4 0xC4 942 #define BK_MACE_C5 0xC5 943 #define BK_MACE_C6 0xC6 944 #define BK_MACE_C7 0xC7 945 #define BK_MACE_C8 0xC8 946 #define BK_MACE_C9 0xC9 947 #define BK_MACE_CA 0xCA 948 #define BK_MACE_CB 0xCB 949 #define BK_MACE_CC 0xCC 950 #define BK_MACE_CD 0xCD 951 #define BK_MACE_CE 0xCE 952 #define BK_MACE_CF 0xCF 953 #define BK_MACE_D0 0xD0 954 #define BK_MACE_D1 0xD1 955 #define BK_MACE_D2 0xD2 956 #define BK_MACE_D3 0xD3 957 #define BK_MACE_D4 0xD4 958 #define BK_MACE_D5 0xD5 959 #define BK_MACE_D6 0xD6 960 #define BK_MACE_D7 0xD7 961 #define BK_MACE_D8 0xD8 962 #define BK_MACE_D9 0xD9 963 #define BK_MACE_DA 0xDA 964 #define BK_MACE_DB 0xDB 965 #define BK_MACE_DC 0xDC 966 #define BK_MACE_DD 0xDD 967 #define BK_MACE_DE 0xDE 968 #define BK_MACE_DF 0xDF 969 #define BK_MACE_E0 0xE0 970 #define BK_MACE_E1 0xE1 971 #define BK_MACE_E2 0xE2 972 #define BK_MACE_E3 0xE3 973 #define BK_MACE_E4 0xE4 974 #define BK_MACE_E5 0xE5 975 #define BK_MACE_E6 0xE6 976 #define BK_MACE_E7 0xE7 977 #define BK_MACE_E8 0xE8 978 #define BK_MACE_E9 0xE9 979 #define BK_MACE_EA 0xEA 980 #define BK_MACE_EB 0xEB 981 #define BK_MACE_EC 0xEC 982 #define BK_MACE_ED 0xED 983 #define BK_MACE_EE 0xEE 984 #define BK_MACE_EF 0xEF 985 #define BK_MACE_F0 0xF0 986 #define BK_MACE_F1 0xF1 987 #define BK_MACE_F2 0xF2 988 #define BK_MACE_F3 0xF3 989 #define BK_MACE_F4 0xF4 990 #define BK_MACE_F5 0xF5 991 #define BK_MACE_F6 0xF6 992 #define BK_MACE_F7 0xF7 993 #define BK_MACE_F8 0xF8 994 #define BK_MACE_F9 0xF9 995 #define BK_MACE_FA 0xFA 996 #define BK_MACE_FB 0xFB 997 #define BK_MACE_FC 0xFC 998 #define BK_MACE_FD 0xFD 999 #define BK_MACE_FE 0xFE 1000 #define BK_MACE_FF 0xFF 1001 1002 1003 //////////////////////////////////////////////////////////////////////////////// 1004 // Comb filter bank 1005 //////////////////////////////////////////////////////////////////////////////// 1006 1007 #define BK_COMB_01 (COMB_REG_BASE+0x01) 1008 #define BK_COMB_02 (COMB_REG_BASE+0x02) 1009 #define BK_COMB_03 (COMB_REG_BASE+0x03) 1010 #define BK_COMB_04 (COMB_REG_BASE+0x04) 1011 #define BK_COMB_05 (COMB_REG_BASE+0x05) 1012 #define BK_COMB_06 (COMB_REG_BASE+0x06) 1013 #define BK_COMB_07 (COMB_REG_BASE+0x07) 1014 #define BK_COMB_08 (COMB_REG_BASE+0x08) 1015 #define BK_COMB_09 (COMB_REG_BASE+0x09) 1016 #define BK_COMB_0A (COMB_REG_BASE+0x0A) 1017 #define BK_COMB_0B (COMB_REG_BASE+0x0B) 1018 #define BK_COMB_0C (COMB_REG_BASE+0x0C) 1019 #define BK_COMB_0D (COMB_REG_BASE+0x0D) 1020 #define BK_COMB_0E (COMB_REG_BASE+0x0E) 1021 #define BK_COMB_0F (COMB_REG_BASE+0x0F) 1022 #define BK_COMB_10 (COMB_REG_BASE+0x10) 1023 #define BK_COMB_11 (COMB_REG_BASE+0x11) 1024 #define BK_COMB_12 (COMB_REG_BASE+0x12) 1025 #define BK_COMB_13 (COMB_REG_BASE+0x13) 1026 #define BK_COMB_14 (COMB_REG_BASE+0x14) 1027 #define BK_COMB_15 (COMB_REG_BASE+0x15) 1028 #define BK_COMB_16 (COMB_REG_BASE+0x16) 1029 #define BK_COMB_17 (COMB_REG_BASE+0x17) 1030 #define BK_COMB_18 (COMB_REG_BASE+0x18) 1031 #define BK_COMB_19 (COMB_REG_BASE+0x19) 1032 #define BK_COMB_1A (COMB_REG_BASE+0x1A) 1033 #define BK_COMB_1B (COMB_REG_BASE+0x1B) 1034 #define BK_COMB_1C (COMB_REG_BASE+0x1C) 1035 #define BK_COMB_1D (COMB_REG_BASE+0x1D) 1036 #define BK_COMB_1E (COMB_REG_BASE+0x1E) 1037 #define BK_COMB_1F (COMB_REG_BASE+0x1F) 1038 #define BK_COMB_20 (COMB_REG_BASE+0x20) 1039 #define BK_COMB_21 (COMB_REG_BASE+0x21) 1040 #define BK_COMB_22 (COMB_REG_BASE+0x22) 1041 #define BK_COMB_23 (COMB_REG_BASE+0x23) 1042 #define BK_COMB_24 (COMB_REG_BASE+0x24) 1043 #define BK_COMB_25 (COMB_REG_BASE+0x25) 1044 #define BK_COMB_26 (COMB_REG_BASE+0x26) 1045 #define BK_COMB_27 (COMB_REG_BASE+0x27) 1046 #define BK_COMB_28 (COMB_REG_BASE+0x28) 1047 #define BK_COMB_29 (COMB_REG_BASE+0x29) 1048 #define BK_COMB_2A (COMB_REG_BASE+0x2A) 1049 #define BK_COMB_2B (COMB_REG_BASE+0x2B) 1050 #define BK_COMB_2C (COMB_REG_BASE+0x2C) 1051 #define BK_COMB_2D (COMB_REG_BASE+0x2D) 1052 #define BK_COMB_2E (COMB_REG_BASE+0x2E) 1053 #define BK_COMB_2F (COMB_REG_BASE+0x2F) 1054 #define BK_COMB_30 (COMB_REG_BASE+0x30) 1055 #define BK_COMB_31 (COMB_REG_BASE+0x31) 1056 #define BK_COMB_32 (COMB_REG_BASE+0x32) 1057 #define BK_COMB_33 (COMB_REG_BASE+0x33) 1058 #define BK_COMB_34 (COMB_REG_BASE+0x34) 1059 #define BK_COMB_35 (COMB_REG_BASE+0x35) 1060 #define BK_COMB_36 (COMB_REG_BASE+0x36) 1061 #define BK_COMB_37 (COMB_REG_BASE+0x37) 1062 #define BK_COMB_38 (COMB_REG_BASE+0x38) 1063 #define BK_COMB_39 (COMB_REG_BASE+0x39) 1064 #define BK_COMB_3A (COMB_REG_BASE+0x3A) 1065 #define BK_COMB_3B (COMB_REG_BASE+0x3B) 1066 #define BK_COMB_3C (COMB_REG_BASE+0x3C) 1067 #define BK_COMB_3D (COMB_REG_BASE+0x3D) 1068 #define BK_COMB_3E (COMB_REG_BASE+0x3E) 1069 #define BK_COMB_3F (COMB_REG_BASE+0x3F) 1070 #define BK_COMB_40 (COMB_REG_BASE+0x40) 1071 #define BK_COMB_41 (COMB_REG_BASE+0x41) 1072 #define BK_COMB_42 (COMB_REG_BASE+0x42) 1073 #define BK_COMB_43 (COMB_REG_BASE+0x43) 1074 #define BK_COMB_44 (COMB_REG_BASE+0x44) 1075 #define BK_COMB_45 (COMB_REG_BASE+0x45) 1076 #define BK_COMB_46 (COMB_REG_BASE+0x46) 1077 #define BK_COMB_47 (COMB_REG_BASE+0x47) 1078 #define BK_COMB_48 (COMB_REG_BASE+0x48) 1079 #define BK_COMB_49 (COMB_REG_BASE+0x49) 1080 #define BK_COMB_4A (COMB_REG_BASE+0x4A) 1081 #define BK_COMB_4B (COMB_REG_BASE+0x4B) 1082 #define BK_COMB_4C (COMB_REG_BASE+0x4C) 1083 #define BK_COMB_4D (COMB_REG_BASE+0x4D) 1084 #define BK_COMB_4E (COMB_REG_BASE+0x4E) 1085 #define BK_COMB_4F (COMB_REG_BASE+0x4F) 1086 #define BK_COMB_50 (COMB_REG_BASE+0x50) 1087 #define BK_COMB_51 (COMB_REG_BASE+0x51) 1088 #define BK_COMB_52 (COMB_REG_BASE+0x52) 1089 #define BK_COMB_53 (COMB_REG_BASE+0x53) 1090 #define BK_COMB_54 (COMB_REG_BASE+0x54) 1091 #define BK_COMB_55 (COMB_REG_BASE+0x55) 1092 #define BK_COMB_56 (COMB_REG_BASE+0x56) 1093 #define BK_COMB_57 (COMB_REG_BASE+0x57) 1094 #define BK_COMB_58 (COMB_REG_BASE+0x58) 1095 #define BK_COMB_59 (COMB_REG_BASE+0x59) 1096 #define BK_COMB_5A (COMB_REG_BASE+0x5A) 1097 #define BK_COMB_5B (COMB_REG_BASE+0x5B) 1098 #define BK_COMB_5C (COMB_REG_BASE+0x5C) 1099 #define BK_COMB_5D (COMB_REG_BASE+0x5D) 1100 #define BK_COMB_5E (COMB_REG_BASE+0x5E) 1101 #define BK_COMB_5F (COMB_REG_BASE+0x5F) 1102 #define BK_COMB_60 (COMB_REG_BASE+0x60) 1103 #define BK_COMB_61 (COMB_REG_BASE+0x61) 1104 #define BK_COMB_62 (COMB_REG_BASE+0x62) 1105 #define BK_COMB_63 (COMB_REG_BASE+0x63) 1106 #define BK_COMB_64 (COMB_REG_BASE+0x64) 1107 #define BK_COMB_65 (COMB_REG_BASE+0x65) 1108 #define BK_COMB_66 (COMB_REG_BASE+0x66) 1109 #define BK_COMB_67 (COMB_REG_BASE+0x67) 1110 #define BK_COMB_68 (COMB_REG_BASE+0x68) 1111 #define BK_COMB_69 (COMB_REG_BASE+0x69) 1112 #define BK_COMB_6A (COMB_REG_BASE+0x6A) 1113 #define BK_COMB_6B (COMB_REG_BASE+0x6B) 1114 #define BK_COMB_6C (COMB_REG_BASE+0x6C) 1115 #define BK_COMB_6D (COMB_REG_BASE+0x6D) 1116 #define BK_COMB_6E (COMB_REG_BASE+0x6E) 1117 #define BK_COMB_6F (COMB_REG_BASE+0x6F) 1118 #define BK_COMB_70 (COMB_REG_BASE+0x70) 1119 #define BK_COMB_71 (COMB_REG_BASE+0x71) 1120 #define BK_COMB_72 (COMB_REG_BASE+0x72) 1121 #define BK_COMB_73 (COMB_REG_BASE+0x73) 1122 #define BK_COMB_74 (COMB_REG_BASE+0x74) 1123 #define BK_COMB_75 (COMB_REG_BASE+0x75) 1124 #define BK_COMB_76 (COMB_REG_BASE+0x76) 1125 #define BK_COMB_77 (COMB_REG_BASE+0x77) 1126 #define BK_COMB_78 (COMB_REG_BASE+0x78) 1127 #define BK_COMB_79 (COMB_REG_BASE+0x79) 1128 #define BK_COMB_7A (COMB_REG_BASE+0x7A) 1129 #define BK_COMB_7B (COMB_REG_BASE+0x7B) 1130 #define BK_COMB_7C (COMB_REG_BASE+0x7C) 1131 #define BK_COMB_7D (COMB_REG_BASE+0x7D) 1132 #define BK_COMB_7E (COMB_REG_BASE+0x7E) 1133 #define BK_COMB_7F (COMB_REG_BASE+0x7F) 1134 #define BK_COMB_80 (COMB_REG_BASE+0x80) 1135 #define BK_COMB_81 (COMB_REG_BASE+0x81) 1136 #define BK_COMB_82 (COMB_REG_BASE+0x82) 1137 #define BK_COMB_83 (COMB_REG_BASE+0x83) 1138 #define BK_COMB_84 (COMB_REG_BASE+0x84) 1139 #define BK_COMB_85 (COMB_REG_BASE+0x85) 1140 #define BK_COMB_86 (COMB_REG_BASE+0x86) 1141 #define BK_COMB_87 (COMB_REG_BASE+0x87) 1142 #define BK_COMB_88 (COMB_REG_BASE+0x88) 1143 #define BK_COMB_89 (COMB_REG_BASE+0x89) 1144 #define BK_COMB_8A (COMB_REG_BASE+0x8A) 1145 #define BK_COMB_8B (COMB_REG_BASE+0x8B) 1146 #define BK_COMB_8C (COMB_REG_BASE+0x8C) 1147 #define BK_COMB_8D (COMB_REG_BASE+0x8D) 1148 #define BK_COMB_8E (COMB_REG_BASE+0x8E) 1149 #define BK_COMB_8F (COMB_REG_BASE+0x8F) 1150 #define BK_COMB_90 (COMB_REG_BASE+0x90) 1151 #define BK_COMB_91 (COMB_REG_BASE+0x91) 1152 #define BK_COMB_92 (COMB_REG_BASE+0x92) 1153 #define BK_COMB_93 (COMB_REG_BASE+0x93) 1154 #define BK_COMB_94 (COMB_REG_BASE+0x94) 1155 #define BK_COMB_95 (COMB_REG_BASE+0x95) 1156 #define BK_COMB_96 (COMB_REG_BASE+0x96) 1157 #define BK_COMB_97 (COMB_REG_BASE+0x97) 1158 #define BK_COMB_98 (COMB_REG_BASE+0x98) 1159 #define BK_COMB_99 (COMB_REG_BASE+0x99) 1160 #define BK_COMB_9A (COMB_REG_BASE+0x9A) 1161 #define BK_COMB_9B (COMB_REG_BASE+0x9B) 1162 #define BK_COMB_9C (COMB_REG_BASE+0x9C) 1163 #define BK_COMB_9D (COMB_REG_BASE+0x9D) 1164 #define BK_COMB_9E (COMB_REG_BASE+0x9E) 1165 #define BK_COMB_9F (COMB_REG_BASE+0x9F) 1166 #define BK_COMB_A0 (COMB_REG_BASE+0xA0) 1167 #define BK_COMB_A1 (COMB_REG_BASE+0xA1) 1168 #define BK_COMB_A2 (COMB_REG_BASE+0xA2) 1169 #define BK_COMB_A3 (COMB_REG_BASE+0xA3) 1170 #define BK_COMB_A4 (COMB_REG_BASE+0xA4) 1171 #define BK_COMB_A5 (COMB_REG_BASE+0xA5) 1172 #define BK_COMB_A6 (COMB_REG_BASE+0xA6) 1173 #define BK_COMB_A7 (COMB_REG_BASE+0xA7) 1174 #define BK_COMB_A8 (COMB_REG_BASE+0xA8) 1175 #define BK_COMB_A9 (COMB_REG_BASE+0xA9) 1176 #define BK_COMB_AA (COMB_REG_BASE+0xAA) 1177 #define BK_COMB_AB (COMB_REG_BASE+0xAB) 1178 #define BK_COMB_AC (COMB_REG_BASE+0xAC) 1179 #define BK_COMB_AD (COMB_REG_BASE+0xAD) 1180 #define BK_COMB_AE (COMB_REG_BASE+0xAE) 1181 #define BK_COMB_AF (COMB_REG_BASE+0xAF) 1182 #define BK_COMB_B0 (COMB_REG_BASE+0xB0) 1183 #define BK_COMB_B1 (COMB_REG_BASE+0xB1) 1184 #define BK_COMB_B2 (COMB_REG_BASE+0xB2) 1185 #define BK_COMB_B3 (COMB_REG_BASE+0xB3) 1186 #define BK_COMB_B4 (COMB_REG_BASE+0xB4) 1187 #define BK_COMB_B5 (COMB_REG_BASE+0xB5) 1188 #define BK_COMB_B6 (COMB_REG_BASE+0xB6) 1189 #define BK_COMB_B7 (COMB_REG_BASE+0xB7) 1190 #define BK_COMB_B8 (COMB_REG_BASE+0xB8) 1191 #define BK_COMB_B9 (COMB_REG_BASE+0xB9) 1192 #define BK_COMB_BA (COMB_REG_BASE+0xBA) 1193 #define BK_COMB_BB (COMB_REG_BASE+0xBB) 1194 #define BK_COMB_BC (COMB_REG_BASE+0xBC) 1195 #define BK_COMB_BD (COMB_REG_BASE+0xBD) 1196 #define BK_COMB_BE (COMB_REG_BASE+0xBE) 1197 #define BK_COMB_BF (COMB_REG_BASE+0xBF) 1198 #define BK_COMB_C0 (COMB_REG_BASE+0xC0) 1199 #define BK_COMB_C1 (COMB_REG_BASE+0xC1) 1200 #define BK_COMB_C2 (COMB_REG_BASE+0xC2) 1201 #define BK_COMB_C3 (COMB_REG_BASE+0xC3) 1202 #define BK_COMB_C4 (COMB_REG_BASE+0xC4) 1203 #define BK_COMB_C5 (COMB_REG_BASE+0xC5) 1204 #define BK_COMB_C6 (COMB_REG_BASE+0xC6) 1205 #define BK_COMB_C7 (COMB_REG_BASE+0xC7) 1206 #define BK_COMB_C8 (COMB_REG_BASE+0xC8) 1207 #define BK_COMB_C9 (COMB_REG_BASE+0xC9) 1208 #define BK_COMB_CA (COMB_REG_BASE+0xCA) 1209 #define BK_COMB_CB (COMB_REG_BASE+0xCB) 1210 #define BK_COMB_CC (COMB_REG_BASE+0xCC) 1211 #define BK_COMB_CD (COMB_REG_BASE+0xCD) 1212 #define BK_COMB_CE (COMB_REG_BASE+0xCE) 1213 #define BK_COMB_CF (COMB_REG_BASE+0xCF) 1214 #define BK_COMB_D0 (COMB_REG_BASE+0xD0) 1215 #define BK_COMB_D1 (COMB_REG_BASE+0xD1) 1216 #define BK_COMB_D2 (COMB_REG_BASE+0xD2) 1217 #define BK_COMB_D3 (COMB_REG_BASE+0xD3) 1218 #define BK_COMB_D4 (COMB_REG_BASE+0xD4) 1219 #define BK_COMB_D5 (COMB_REG_BASE+0xD5) 1220 #define BK_COMB_D6 (COMB_REG_BASE+0xD6) 1221 #define BK_COMB_D7 (COMB_REG_BASE+0xD7) 1222 #define BK_COMB_D8 (COMB_REG_BASE+0xD8) 1223 #define BK_COMB_D9 (COMB_REG_BASE+0xD9) 1224 #define BK_COMB_DA (COMB_REG_BASE+0xDA) 1225 #define BK_COMB_DB (COMB_REG_BASE+0xDB) 1226 #define BK_COMB_DC (COMB_REG_BASE+0xDC) 1227 #define BK_COMB_DD (COMB_REG_BASE+0xDD) 1228 #define BK_COMB_DE (COMB_REG_BASE+0xDE) 1229 #define BK_COMB_DF (COMB_REG_BASE+0xDF) 1230 #define BK_COMB_E0 (COMB_REG_BASE+0xE0) 1231 #define BK_COMB_E1 (COMB_REG_BASE+0xE1) 1232 #define BK_COMB_E2 (COMB_REG_BASE+0xE2) 1233 #define BK_COMB_E3 (COMB_REG_BASE+0xE3) 1234 #define BK_COMB_E4 (COMB_REG_BASE+0xE4) 1235 #define BK_COMB_E5 (COMB_REG_BASE+0xE5) 1236 #define BK_COMB_E6 (COMB_REG_BASE+0xE6) 1237 #define BK_COMB_E7 (COMB_REG_BASE+0xE7) 1238 #define BK_COMB_E8 (COMB_REG_BASE+0xE8) 1239 #define BK_COMB_E9 (COMB_REG_BASE+0xE9) 1240 #define BK_COMB_EA (COMB_REG_BASE+0xEA) 1241 #define BK_COMB_EB (COMB_REG_BASE+0xEB) 1242 #define BK_COMB_EC (COMB_REG_BASE+0xEC) 1243 #define BK_COMB_ED (COMB_REG_BASE+0xED) 1244 #define BK_COMB_EE (COMB_REG_BASE+0xEE) 1245 #define BK_COMB_EF (COMB_REG_BASE+0xEF) 1246 #define BK_COMB_F0 (COMB_REG_BASE+0xF0) 1247 #define BK_COMB_F1 (COMB_REG_BASE+0xF1) 1248 #define BK_COMB_F2 (COMB_REG_BASE+0xF2) 1249 #define BK_COMB_F3 (COMB_REG_BASE+0xF3) 1250 #define BK_COMB_F4 (COMB_REG_BASE+0xF4) 1251 #define BK_COMB_F5 (COMB_REG_BASE+0xF5) 1252 #define BK_COMB_F6 (COMB_REG_BASE+0xF6) 1253 #define BK_COMB_F7 (COMB_REG_BASE+0xF7) 1254 #define BK_COMB_F8 (COMB_REG_BASE+0xF8) 1255 #define BK_COMB_F9 (COMB_REG_BASE+0xF9) 1256 #define BK_COMB_FA (COMB_REG_BASE+0xFA) 1257 #define BK_COMB_FB (COMB_REG_BASE+0xFB) 1258 #define BK_COMB_FC (COMB_REG_BASE+0xFC) 1259 #define BK_COMB_FD (COMB_REG_BASE+0xFD) 1260 #define BK_COMB_FE (COMB_REG_BASE+0xFE) 1261 #define BK_COMB_FF (COMB_REG_BASE+0xFF) 1262 1263 1264 //////////////////////////////////////////////////////////////////////////////// 1265 // SECAM register 1266 //////////////////////////////////////////////////////////////////////////////// 1267 #define BK_SECAM_01 (SCM_REG_BASE+0x01) 1268 #define BK_SECAM_02 (SCM_REG_BASE+0x02) 1269 #define BK_SECAM_03 (SCM_REG_BASE+0x03) 1270 #define BK_SECAM_04 (SCM_REG_BASE+0x04) 1271 #define BK_SECAM_05 (SCM_REG_BASE+0x05) 1272 #define BK_SECAM_06 (SCM_REG_BASE+0x06) 1273 #define BK_SECAM_07 (SCM_REG_BASE+0x07) 1274 #define BK_SECAM_08 (SCM_REG_BASE+0x08) 1275 #define BK_SECAM_09 (SCM_REG_BASE+0x09) 1276 #define BK_SECAM_0A (SCM_REG_BASE+0x0A) 1277 #define BK_SECAM_0B (SCM_REG_BASE+0x0B) 1278 #define BK_SECAM_0C (SCM_REG_BASE+0x0C) 1279 #define BK_SECAM_0D (SCM_REG_BASE+0x0D) 1280 #define BK_SECAM_0E (SCM_REG_BASE+0x0E) 1281 #define BK_SECAM_0F (SCM_REG_BASE+0x0F) 1282 #define BK_SECAM_10 (SCM_REG_BASE+0x10) 1283 #define BK_SECAM_11 (SCM_REG_BASE+0x11) 1284 #define BK_SECAM_12 (SCM_REG_BASE+0x12) 1285 #define BK_SECAM_13 (SCM_REG_BASE+0x13) 1286 #define BK_SECAM_14 (SCM_REG_BASE+0x14) 1287 #define BK_SECAM_15 (SCM_REG_BASE+0x15) 1288 #define BK_SECAM_16 (SCM_REG_BASE+0x16) 1289 #define BK_SECAM_17 (SCM_REG_BASE+0x17) 1290 #define BK_SECAM_18 (SCM_REG_BASE+0x18) 1291 #define BK_SECAM_19 (SCM_REG_BASE+0x19) 1292 #define BK_SECAM_1A (SCM_REG_BASE+0x1A) 1293 #define BK_SECAM_1B (SCM_REG_BASE+0x1B) 1294 #define BK_SECAM_1C (SCM_REG_BASE+0x1C) 1295 #define BK_SECAM_1D (SCM_REG_BASE+0x1D) 1296 #define BK_SECAM_1E (SCM_REG_BASE+0x1E) 1297 #define BK_SECAM_1F (SCM_REG_BASE+0x1F) 1298 #define BK_SECAM_20 (SCM_REG_BASE+0x20) 1299 #define BK_SECAM_21 (SCM_REG_BASE+0x21) 1300 #define BK_SECAM_22 (SCM_REG_BASE+0x22) 1301 #define BK_SECAM_23 (SCM_REG_BASE+0x23) 1302 #define BK_SECAM_24 (SCM_REG_BASE+0x24) 1303 #define BK_SECAM_25 (SCM_REG_BASE+0x25) 1304 #define BK_SECAM_26 (SCM_REG_BASE+0x26) 1305 #define BK_SECAM_27 (SCM_REG_BASE+0x27) 1306 #define BK_SECAM_28 (SCM_REG_BASE+0x28) 1307 #define BK_SECAM_29 (SCM_REG_BASE+0x29) 1308 #define BK_SECAM_2A (SCM_REG_BASE+0x2A) 1309 #define BK_SECAM_2B (SCM_REG_BASE+0x2B) 1310 #define BK_SECAM_2C (SCM_REG_BASE+0x2C) 1311 #define BK_SECAM_2D (SCM_REG_BASE+0x2D) 1312 #define BK_SECAM_2E (SCM_REG_BASE+0x2E) 1313 #define BK_SECAM_2F (SCM_REG_BASE+0x2F) 1314 #define BK_SECAM_30 (SCM_REG_BASE+0x30) 1315 #define BK_SECAM_31 (SCM_REG_BASE+0x31) 1316 #define BK_SECAM_32 (SCM_REG_BASE+0x32) 1317 #define BK_SECAM_33 (SCM_REG_BASE+0x33) 1318 #define BK_SECAM_34 (SCM_REG_BASE+0x34) 1319 #define BK_SECAM_35 (SCM_REG_BASE+0x35) 1320 #define BK_SECAM_36 (SCM_REG_BASE+0x36) 1321 #define BK_SECAM_37 (SCM_REG_BASE+0x37) 1322 #define BK_SECAM_38 (SCM_REG_BASE+0x38) 1323 #define BK_SECAM_39 (SCM_REG_BASE+0x39) 1324 #define BK_SECAM_3A (SCM_REG_BASE+0x3A) 1325 #define BK_SECAM_3B (SCM_REG_BASE+0x3B) 1326 #define BK_SECAM_3C (SCM_REG_BASE+0x3C) 1327 #define BK_SECAM_3D (SCM_REG_BASE+0x3D) 1328 #define BK_SECAM_3E (SCM_REG_BASE+0x3E) 1329 #define BK_SECAM_3F (SCM_REG_BASE+0x3F) 1330 1331 //////////////////////////////////////////////////////////////////////////////// 1332 // VBI register 1333 //////////////////////////////////////////////////////////////////////////////// 1334 #define BK_VBI_2A (VBI_REG_BASE+0x2A) 1335 #define BK_VBI_41 (VBI_REG_BASE+0x41) 1336 #define BK_VBI_45 (VBI_REG_BASE+0x45) 1337 #define BK_VBI_46 (VBI_REG_BASE+0x46) 1338 #define BK_VBI_4A (VBI_REG_BASE+0x4A) 1339 #define BK_VBI_4F (VBI_REG_BASE+0x4F) 1340 #define BK_VBI_50 (VBI_REG_BASE+0x50) 1341 #define BK_VBI_51 (VBI_REG_BASE+0x51) 1342 #define BK_VBI_55 (VBI_REG_BASE+0x55) 1343 #define BK_VBI_56 (VBI_REG_BASE+0x56) 1344 #define BK_VBI_57 (VBI_REG_BASE+0x57) 1345 #define BK_VBI_58 (VBI_REG_BASE+0x58) 1346 #define BK_VBI_59 (VBI_REG_BASE+0x59) 1347 #define BK_VBI_5A (VBI_REG_BASE+0x5A) 1348 #define BK_VBI_5B (VBI_REG_BASE+0x5B) 1349 #define BK_VBI_5C (VBI_REG_BASE+0x5C) 1350 #define BK_VBI_5D (VBI_REG_BASE+0x5D) 1351 #define BK_VBI_5E (VBI_REG_BASE+0x5E) 1352 #define BK_VBI_5F (VBI_REG_BASE+0x5F) 1353 #define BK_VBI_70 (VBI_REG_BASE+0x70) 1354 #define BK_VBI_71 (VBI_REG_BASE+0x71) 1355 #define BK_VBI_72 (VBI_REG_BASE+0x72) 1356 #define BK_VBI_77 (VBI_REG_BASE+0x77) 1357 #define BK_VBI_7C (VBI_REG_BASE+0x7C) 1358 #define BK_VBI_7D (VBI_REG_BASE+0x7D) 1359 #define BK_VBI_7E (VBI_REG_BASE+0x7E) 1360 #define BK_VBI_7F (VBI_REG_BASE+0x7F) 1361 #define BK_VBI_81 (VBI_REG_BASE+0x81) 1362 #define BK_VBI_82 (VBI_REG_BASE+0x82) 1363 #define BK_VBI_83 (VBI_REG_BASE+0x83) 1364 #define BK_VBI_86 (VBI_REG_BASE+0x86) 1365 #define BK_VBI_89 (VBI_REG_BASE+0x89) 1366 #define BK_VBI_8A (VBI_REG_BASE+0x8A) 1367 #define BK_VBI_8B (VBI_REG_BASE+0x8B) 1368 #define BK_VBI_8D (VBI_REG_BASE+0x8D) 1369 #define BK_VBI_91 (VBI_REG_BASE+0x91) 1370 #define BK_VBI_92 (VBI_REG_BASE+0x92) 1371 #define BK_VBI_99 (VBI_REG_BASE+0x99) 1372 #define BK_VBI_9A (VBI_REG_BASE+0x9A) 1373 #define BK_VBI_AD (VBI_REG_BASE+0xAD) 1374 #define BK_VBI_AE (VBI_REG_BASE+0xAE) 1375 #define BK_VBI_AF (VBI_REG_BASE+0xAF) 1376 #define BK_VBI_B7 (VBI_REG_BASE+0xB7) 1377 #define BK_VBI_B8 (VBI_REG_BASE+0xB8) 1378 #define BK_VBI_BB (VBI_REG_BASE+0xBB) 1379 #define BK_VBI_C4 (VBI_REG_BASE+0xC4) 1380 #define BK_VBI_CA (VBI_REG_BASE+0xCA) 1381 #define BK_VBI_CB (VBI_REG_BASE+0xCB) 1382 #define BK_VBI_CC (VBI_REG_BASE+0xCC) 1383 #define BK_VBI_CD (VBI_REG_BASE+0xCD) 1384 #define BK_VBI_CE (VBI_REG_BASE+0xCE) 1385 1386 #define REG_ADC_ATOP_38_L (REG_ADC_ATOP_BASE + 0x70) 1387 #define REG_ADC_ATOP_38_H (REG_ADC_ATOP_BASE + 0x71) 1388 #define REG_ADC_ATOP_39_L (REG_ADC_ATOP_BASE + 0x72) 1389 #define REG_ADC_ATOP_39_H (REG_ADC_ATOP_BASE + 0x73) 1390 #define REG_ADC_ATOP_3A_L (REG_ADC_ATOP_BASE + 0x74) 1391 #define REG_ADC_ATOP_3A_H (REG_ADC_ATOP_BASE + 0x75) 1392 #define REG_ADC_ATOP_3B_L (REG_ADC_ATOP_BASE + 0x76) 1393 #define REG_ADC_ATOP_3B_H (REG_ADC_ATOP_BASE + 0x77) 1394 //------------------------------------------------------------------------------ 1395 // chip top 1396 //------------------------------------------------------------------------------ 1397 1398 #define REG_CKG_FCLK 0x1E35 1399 #define CKG_FCLK_GATED (1 << 5) //BIT(5) 1400 #define CKG_FCLK_INVERT (1 << 1) //BIT(1) 1401 #define CKG_FCLK_MASK 0x3C //(BIT(5) | BIT(4) | BIT(3) | BIT(2)) 1402 #define CKG_FCLK_170MHZ (0 << 2) 1403 #define CKG_FCLK_CLK_MIU (1 << 2) 1404 #define CKG_FCLK_CLK_ODCLK (2 << 2) 1405 #define CKG_FCLK_216MHZ (3 << 2) 1406 #define CKG_FCLK_CLK_IDCLK2 (4 << 2) 1407 #define CKG_FCLK_SCPLL (5 << 2) 1408 #define CKG_FCLK_0 (6 << 2) 1409 #define CKG_FCLK_XTAL (7 << 2) 1410 #define CKG_FCLK_XTAL_ (8 << 2) 1411 1412 #define REG_CKG_IDCLK2 0x1E3F 1413 #define CKG_IDCLK2_GATED (1 << 0) 1414 #define CKG_IDCLK2_INVERT (1 << 1) 1415 #define CKG_IDCLK2_MASK 0x3C //BMASK(5:2) // (BIT5 | BIT4 | BIT3 | BIT2) 1416 #define CKG_IDCLK2_CLK_ADC (0 << 2) 1417 #define CKG_IDCLK2_CLK_DVI (1 << 2) 1418 #define CKG_IDCLK2_CLK_VD (2 << 2) 1419 #define CKG_IDCLK2_CLK_DC0 (3 << 2) 1420 #define CKG_IDCLK2_1 (4 << 2) 1421 #define CKG_IDCLK2_CLK_EXT_DI (5 << 2) 1422 #define CKG_IDCLK2_CLK_VD_ADC (6 << 2) 1423 #define CKG_IDCLK2_0 (7 << 2) 1424 #define CKG_IDCLK2_XTAL (8 << 2) 1425 1426 #define REG_CKG_ODCLK 0x1E37 1427 #define CKG_ODCLK_GATED (1 << 0) 1428 #define CKG_ODCLK_INVERT (1 << 1) 1429 #define CKG_ODCLK_MASK 0x3C //(BIT5 | BIT4 | BIT3 | BIT2) 1430 #define CKG_ODCLK_CLK_ADC (0 << 2) 1431 #define CKG_ODCLK_CLK_DVI (1 << 2) 1432 #define CKG_ODCLK_CLK_VD (2 << 2) 1433 #define CKG_ODCLK_CLK_MPEG0 (3 << 2) 1434 #define CKG_ODCLK_1 (4 << 2) 1435 #define CKG_ODCLK_CLK_EXT_DI (5 << 2) 1436 #define CKG_ODCLK_XTAL (6 << 2) 1437 #define CKG_ODCLK_CLK_LPLL (7 << 2) 1438 #define CKG_ODCLK_XTAL_ (8 << 2) 1439 1440 #endif // ANALOG_REG_H 1441