1 /* 2 * Copyright 2022 Rockchip Electronics Co. LTD 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __HAL_VDPU382_VP9D_H__ 18 #define __HAL_VDPU382_VP9D_H__ 19 20 #include "rk_type.h" 21 #include "vdpu382_com.h" 22 23 24 typedef struct Vdpu382RegVp9dParam_t { 25 struct SWREG64_VP9_SET { 26 RK_U32 cprheader_offset : 16; 27 RK_U32 reserve : 16; 28 } reg64; 29 30 struct SWREG65_CUR_POC { 31 RK_U32 cur_poc : 32; 32 } reg65; 33 34 RK_U32 reg66; 35 36 struct SWREG67_74_VP9_SEGID_GRP { 37 RK_U32 segid_abs_delta : 1; 38 RK_U32 segid_frame_qp_delta_en : 1; 39 RK_U32 segid_frame_qp_delta : 9; 40 RK_U32 segid_frame_loopfitler_value_en : 1; 41 RK_U32 segid_frame_loopfilter_value : 7; 42 RK_U32 segid_referinfo_en : 1; 43 RK_U32 segid_referinfo : 2; 44 RK_U32 segid_frame_skip_en : 1; 45 RK_U32 reserve : 9; 46 } reg67_74[8]; 47 48 struct SWREG75_VP9_INFO_LASTFRAME { 49 RK_U32 mode_deltas_lastframe : 14; 50 RK_U32 vp9_segment_id_clear : 1; 51 RK_U32 vp9_segment_id_update : 1; 52 RK_U32 segmentation_enable_lstframe : 1; 53 RK_U32 last_show_frame : 1; 54 RK_U32 last_intra_only : 1; 55 RK_U32 last_widthheight_eqcur : 1; 56 RK_U32 color_space_lastkeyframe : 3; 57 RK_U32 reserve1 : 9; 58 } reg75; 59 60 struct SWREG76_VP9_CPRHEADER_CONFIG { 61 RK_U32 tx_mode : 3; 62 RK_U32 frame_reference_mode : 2; 63 RK_U32 reserve : 27; 64 } reg76; 65 66 struct SWREG77_VP9_INTERCMD_NUM { 67 RK_U32 intercmd_num : 24; 68 RK_U32 reserve : 8; 69 } reg77; 70 71 struct SWREG78_VP9_LASTTILE_SIZE { 72 RK_U32 lasttile_size : 24; 73 RK_U32 reserve : 8; 74 } reg78; 75 76 struct SWREG79_VP9_LASTF_Y_HOR_VIRSTRIDE { 77 RK_U32 lastfy_hor_virstride : 16; 78 RK_U32 reserve : 16; 79 } reg79; 80 81 struct SWREG80_VP9_LASTF_UV_HOR_VIRSTRIDE { 82 RK_U32 lastfuv_hor_virstride : 16; 83 RK_U32 reserve : 16; 84 } reg80; 85 86 struct SWREG81_VP9_GOLDENF_Y_HOR_VIRSTRIDE { 87 RK_U32 goldenfy_hor_virstride : 16; 88 RK_U32 reserve : 16; 89 } reg81; 90 91 struct SWREG82_VP9_GOLDENF_UV_HOR_VIRSTRIDE { 92 RK_U32 goldenfuv_hor_virstride : 16; 93 RK_U32 reserve : 16; 94 } reg82; 95 96 struct SWREG83_VP9_ALTREFF_Y_HOR_VIRSTRIDE { 97 RK_U32 altreffy_hor_virstride : 16; 98 RK_U32 reserve : 16; 99 } reg83; 100 101 struct SWREG84_VP9_ALTREFF_UV_HOR_VIRSTRIDE { 102 RK_U32 altreffuv_hor_virstride : 16; 103 RK_U32 reserve : 16; 104 } reg84; 105 106 struct SWREG85_VP9_LASTF_Y_VIRSTRIDE { 107 RK_U32 lastfy_virstride : 28; 108 RK_U32 reserve : 4; 109 } reg85; 110 111 struct SWREG86_VP9_GOLDEN_Y_VIRSTRIDE { 112 RK_U32 goldeny_virstride : 28; 113 RK_U32 reserve : 4; 114 } reg86; 115 116 struct SWREG87_VP9_ALTREF_Y_VIRSTRIDE { 117 RK_U32 altrefy_virstride : 28; 118 RK_U32 reserve : 4; 119 } reg87; 120 121 struct SWREG88_VP9_LREF_HOR_SCALE { 122 RK_U32 lref_hor_scale : 16; 123 RK_U32 reserve : 16; 124 } reg88; 125 126 struct SWREG89_VP9_LREF_VER_SCALE { 127 RK_U32 lref_ver_scale : 16; 128 RK_U32 reserve : 16; 129 } reg89; 130 131 struct SWREG90_VP9_GREF_HOR_SCALE { 132 RK_U32 gref_hor_scale : 16; 133 RK_U32 reserve : 16; 134 } reg90; 135 136 struct SWREG91_VP9_GREF_VER_SCALE { 137 RK_U32 gref_ver_scale : 16; 138 RK_U32 reserve : 16; 139 } reg91; 140 141 struct SWREG92_VP9_AREF_HOR_SCALE { 142 RK_U32 aref_hor_scale : 16; 143 RK_U32 reserve : 16; 144 } reg92; 145 146 struct SWREG93_VP9_AREF_VER_SCALE { 147 RK_U32 aref_ver_scale : 16; 148 RK_U32 reserve : 16; 149 } reg93; 150 151 struct SWREG94_VP9_REF_DELTAS_LASTFRAME { 152 RK_U32 ref_deltas_lastframe : 28; 153 RK_U32 reserve : 4; 154 } reg94; 155 156 struct SWREG95_LAST_POC { 157 RK_U32 last_poc : 32; 158 } reg95; 159 160 struct SWREG96_GOLDEN_POC { 161 RK_U32 golden_poc : 32; 162 } reg96; 163 164 struct SWREG97_ALTREF_POC { 165 RK_U32 altref_poc : 32; 166 } reg97; 167 168 struct SWREG98_COF_REF_POC { 169 RK_U32 col_ref_poc : 32; 170 } reg98; 171 172 struct SWREG99_PROB_REF_POC { 173 RK_U32 prob_ref_poc : 32; 174 } reg99; 175 176 struct SWREG100_SEGID_REF_POC { 177 RK_U32 segid_ref_poc : 32; 178 } reg100; 179 180 RK_U32 reg101_102_no_use[2]; 181 182 struct SWREG103_VP9_PROB_EN { 183 RK_U32 reserve : 20; 184 RK_U32 prob_update_en : 1; 185 RK_U32 refresh_en : 1; 186 RK_U32 prob_save_en : 1; 187 RK_U32 intra_only_flag : 1; 188 189 RK_U32 txfmmode_rfsh_en : 1; 190 RK_U32 ref_mode_rfsh_en : 1; 191 RK_U32 single_ref_rfsh_en : 1; 192 RK_U32 comp_ref_rfsh_en : 1; 193 194 RK_U32 interp_filter_switch_en : 1; 195 RK_U32 allow_high_precision_mv : 1; 196 RK_U32 last_key_frame_flag : 1; 197 RK_U32 inter_coef_rfsh_flag : 1; 198 } reg103; 199 200 RK_U32 reg104_no_use; 201 202 struct SWREG105_VP9CNT_UPD_EN_AVS2_HEADLEN { 203 RK_U32 avs2_head_len : 4; 204 RK_U32 count_update_en : 1; 205 RK_U32 reserve : 27; 206 } reg105; 207 208 struct SWREG106_VP9_FRAME_WIDTH_LAST { 209 RK_U32 framewidth_last : 16; 210 RK_U32 reserve : 16; 211 } reg106; 212 213 struct SWREG107_VP9_FRAME_HEIGHT_LAST { 214 RK_U32 frameheight_last : 16; 215 RK_U32 reserve : 16; 216 } reg107; 217 218 struct SWREG108_VP9_FRAME_WIDTH_GOLDEN { 219 RK_U32 framewidth_golden : 16; 220 RK_U32 reserve : 16; 221 } reg108; 222 223 struct SWREG109_VP9_FRAME_HEIGHT_GOLDEN { 224 RK_U32 frameheight_golden : 16; 225 RK_U32 reserve : 16; 226 } reg109; 227 228 struct SWREG110_VP9_FRAME_WIDTH_ALTREF { 229 RK_U32 framewidth_alfter : 16; 230 RK_U32 reserve : 16; 231 } reg110; 232 233 struct SWREG111_VP9_FRAME_HEIGHT_ALTREF { 234 RK_U32 frameheight_alfter : 16; 235 RK_U32 reserve : 16; 236 } reg111; 237 238 struct SWREG112_ERROR_REF_INFO { 239 RK_U32 ref_error_field : 1; 240 RK_U32 ref_error_topfield : 1; 241 RK_U32 ref_error_topfield_used : 1; 242 RK_U32 ref_error_botfield_used : 1; 243 RK_U32 reserve : 28; 244 } reg112; 245 246 } Vdpu382RegVp9dParam; 247 248 typedef struct Vdpu382RegVp9dAddr_t { 249 250 RK_U32 reg160_delta_prob_base; 251 252 RK_U32 reg161_pps_base; 253 254 RK_U32 reg162_last_prob_base; 255 256 RK_U32 reg163_rps_base; 257 258 RK_U32 reg164_ref_last_base; 259 260 RK_U32 reg165_ref_golden_base; 261 262 RK_U32 reg166_ref_alfter_base; 263 264 RK_U32 reg167_count_prob_base; 265 266 RK_U32 reg168_segidlast_base; 267 268 RK_U32 reg169_segidcur_base; 269 270 RK_U32 reg170_ref_colmv_base; 271 272 RK_U32 reg171_intercmd_base; 273 274 RK_U32 reg172_update_prob_wr_base; 275 276 RK_U32 reg173_179_no_use[7]; 277 278 RK_U32 reg180_scanlist_base; 279 280 RK_U32 reg181_196_ref_colmv_base[16]; 281 282 RK_U32 reg197_cabactbl_base; 283 284 RK_U32 reg198_scale_down_luma_base; 285 286 RK_U32 reg199_scale_down_chorme_base; 287 288 RK_U32 reg200_204reserve[5]; 289 290 struct SWREG205_DEBUG_INFO { 291 RK_U32 force_softreset_valid : 1; 292 RK_U32 force_mmureset_valid : 1; 293 RK_U32 reserve0 : 2; 294 RK_U32 error_auto_rst_disable : 1; 295 RK_U32 right_auto_rst_disable : 1; 296 RK_U32 buf_empty_security_en : 1; 297 RK_U32 coord_realtime_report_en : 1; 298 299 RK_U32 fetchcmd_merge_dis : 1; 300 RK_U32 dec_timeout_dis : 1; 301 RK_U32 reserve1 : 2; 302 RK_U32 force_busidle_req : 1; 303 RK_U32 mmu_force_busidle_req : 1; 304 RK_U32 mmu_sel : 1; 305 RK_U32 reserve2 : 17; 306 307 } reg205; 308 } Vdpu382RegVp9dAddr; 309 310 typedef struct Vdpu382Vp9dRegSet_t { 311 Vdpu382RegCommon common; 312 Vdpu382RegVp9dParam vp9d_param; 313 Vdpu382RegCommonAddr common_addr; 314 Vdpu382RegVp9dAddr vp9d_addr; 315 Vdpu382RegIrqStatus irq_status; 316 Vdpu382RegStatistic statistic; 317 } Vdpu382Vp9dRegSet; 318 319 #endif /* __HAL_VDPU382_VP9D_H__ */