1 /* 2 * Copyright 2022 Rockchip Electronics Co. LTD 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __VDPU382_H265D_H__ 18 #define __VDPU382_H265D_H__ 19 20 #include "vdpu382_com.h" 21 22 typedef struct Vdpu382RegH265d_t { 23 struct SWREG64_H26X_SET { 24 RK_U32 h26x_frame_orslice : 1; 25 RK_U32 h26x_rps_mode : 1; 26 RK_U32 h26x_stream_mode : 1; 27 RK_U32 h26x_stream_lastpacket : 1; 28 RK_U32 h264_firstslice_flag : 1; 29 RK_U32 reserve : 27; 30 } reg64; 31 32 struct SWREG65_CUR_POC { 33 RK_U32 cur_top_poc : 32; 34 } reg65; 35 36 struct SWREG66_H264_CUR_POC1 { 37 RK_U32 cur_bot_poc : 32; 38 } reg66; 39 40 RK_U32 reg67_82_ref_poc[16]; 41 42 43 struct SWREG83_98_H264_REF_POC { 44 RK_U32 ref_poc : 32; 45 } ref_poc_no_use[16]; 46 47 /* struct SWREG99_HEVC_REF_VALID{ 48 RK_U32 hevc_ref_valid : 15; 49 RK_U32 reserve : 17; 50 }hevc_ref_valid; */ 51 52 struct SWREG99_HEVC_REF_VALID { 53 RK_U32 hevc_ref_valid_0 : 1; 54 RK_U32 hevc_ref_valid_1 : 1; 55 RK_U32 hevc_ref_valid_2 : 1; 56 RK_U32 hevc_ref_valid_3 : 1; 57 RK_U32 reserve0 : 4; 58 RK_U32 hevc_ref_valid_4 : 1; 59 RK_U32 hevc_ref_valid_5 : 1; 60 RK_U32 hevc_ref_valid_6 : 1; 61 RK_U32 hevc_ref_valid_7 : 1; 62 RK_U32 reserve1 : 4; 63 RK_U32 hevc_ref_valid_8 : 1; 64 RK_U32 hevc_ref_valid_9 : 1; 65 RK_U32 hevc_ref_valid_10 : 1; 66 RK_U32 hevc_ref_valid_11 : 1; 67 RK_U32 reserve2 : 4; 68 RK_U32 hevc_ref_valid_12 : 1; 69 RK_U32 hevc_ref_valid_13 : 1; 70 RK_U32 hevc_ref_valid_14 : 1; 71 RK_U32 reserve3 : 5; 72 } reg99; 73 74 RK_U32 reg100_102_no_use[3]; 75 76 struct SWREG103_HEVC_MVC0 { 77 RK_U32 ref_pic_layer_same_with_cur : 16; 78 RK_U32 reserve : 16; 79 } reg103; 80 81 struct SWREG104_HEVC_MVC1 { 82 RK_U32 poc_lsb_not_present_flag : 1; 83 RK_U32 num_direct_ref_layers : 6; 84 RK_U32 reserve0 : 1; 85 86 RK_U32 num_reflayer_pics : 6; 87 RK_U32 default_ref_layers_active_flag : 1; 88 RK_U32 max_one_active_ref_layer_flag : 1; 89 90 RK_U32 poc_reset_info_present_flag : 1; 91 RK_U32 vps_poc_lsb_aligned_flag : 1; 92 RK_U32 mvc_poc15_valid_flag : 1; 93 RK_U32 reserve1 : 13; 94 } reg104; 95 96 struct SWREG105_111_NO_USE_REGS { 97 RK_U32 no_use_regs[7]; 98 } no_use_regs; 99 100 struct SWREG112_ERROR_REF_INFO { 101 RK_U32 avs2_ref_error_field : 1; 102 RK_U32 avs2_ref_error_topfield : 1; 103 RK_U32 ref_error_topfield_used : 1; 104 RK_U32 ref_error_botfield_used : 1; 105 RK_U32 reserve : 28; 106 } reg112; 107 108 } Vdpu382RegH265d; 109 110 typedef struct Vdpu382RegH265dAddr_t { 111 struct SWREG160_VP9_DELTA_PROB_BASE { 112 RK_U32 vp9_delta_prob_base : 32; 113 } reg160_no_use; 114 115 RK_U32 reg161_pps_base; 116 117 RK_U32 reg162_no_use; 118 119 RK_U32 reg163_rps_base; 120 121 RK_U32 reg164_179_ref_base[16]; 122 123 RK_U32 reg180_scanlist_addr; 124 125 RK_U32 reg181_196_colmv_base[16]; 126 127 RK_U32 reg197_cabactbl_base; 128 129 RK_U32 reg198_scale_down_luma_base; 130 131 RK_U32 reg199_scale_down_chorme_base; 132 } Vdpu382RegH265dAddr; 133 134 typedef struct Vdpu382H265dHighPoc_t { 135 /* SWREG200 */ 136 struct SWREG200_REF0_7_POC_HIGHBIT { 137 RK_U32 ref0_poc_highbit : 4; 138 RK_U32 ref1_poc_highbit : 4; 139 RK_U32 ref2_poc_highbit : 4; 140 RK_U32 ref3_poc_highbit : 4; 141 RK_U32 ref4_poc_highbit : 4; 142 RK_U32 ref5_poc_highbit : 4; 143 RK_U32 ref6_poc_highbit : 4; 144 RK_U32 ref7_poc_highbit : 4; 145 } reg200; 146 struct SWREG201_REF8_15_POC_HIGHBIT { 147 RK_U32 ref8_poc_highbit : 4; 148 RK_U32 ref9_poc_highbit : 4; 149 RK_U32 ref10_poc_highbit : 4; 150 RK_U32 ref11_poc_highbit : 4; 151 RK_U32 ref12_poc_highbit : 4; 152 RK_U32 ref13_poc_highbit : 4; 153 RK_U32 ref14_poc_highbit : 4; 154 RK_U32 ref15_poc_highbit : 4; 155 } reg201; 156 struct SWREG200_REF16_23_POC_HIGHBIT { 157 RK_U32 ref16_poc_highbit : 4; 158 RK_U32 ref17_poc_highbit : 4; 159 RK_U32 ref18_poc_highbit : 4; 160 RK_U32 ref19_poc_highbit : 4; 161 RK_U32 ref20_poc_highbit : 4; 162 RK_U32 ref21_poc_highbit : 4; 163 RK_U32 ref22_poc_highbit : 4; 164 RK_U32 ref23_poc_highbit : 4; 165 } reg202; 166 struct SWREG200_REF24_31_POC_HIGHBIT { 167 RK_U32 ref24_poc_highbit : 4; 168 RK_U32 ref25_poc_highbit : 4; 169 RK_U32 ref26_poc_highbit : 4; 170 RK_U32 ref27_poc_highbit : 4; 171 RK_U32 ref28_poc_highbit : 4; 172 RK_U32 ref29_poc_highbit : 4; 173 RK_U32 ref30_poc_highbit : 4; 174 RK_U32 ref31_poc_highbit : 4; 175 } reg203; 176 struct SWREG200_CUR_POC_HIGHBIT { 177 RK_U32 cur_poc_highbit : 4; 178 RK_U32 reserver : 28; 179 } reg204; 180 181 struct SWREG205_DEBUG_INFO { 182 RK_U32 force_softreset_valid : 1; 183 RK_U32 force_mmureset_valid : 1; 184 RK_U32 reserve0 : 2; 185 RK_U32 error_auto_rst_disable : 1; 186 RK_U32 right_auto_rst_disable : 1; 187 RK_U32 buf_empty_security_en : 1; 188 RK_U32 coord_realtime_report_en : 1; 189 190 RK_U32 fetchcmd_merge_dis : 1; 191 RK_U32 dec_timeout_dis : 1; 192 RK_U32 reg_cfg_wr_dis : 1; 193 RK_U32 reserve1 : 1; 194 RK_U32 force_busidle_req : 1; 195 RK_U32 mmu_force_busidle_req : 1; 196 RK_U32 mmu_sel : 1; 197 RK_U32 reserve2 : 17; 198 199 } reg205; 200 } Vdpu382H2645HighPoc_t; 201 202 typedef struct Vdpu382H265dRegSet_t { 203 Vdpu382RegCommon common; 204 Vdpu382RegH265d h265d_param; 205 Vdpu382RegCommonAddr common_addr; 206 Vdpu382RegH265dAddr h265d_addr; 207 Vdpu382H2645HighPoc_t highpoc; 208 Vdpu382RegIrqStatus irq_status; 209 Vdpu382RegStatistic statistic; 210 } Vdpu382H265dRegSet; 211 212 #endif /* __VDPU382_H265D_H__ */ 213