1 /* 2 * Copyright 2022 Rockchip Electronics Co. LTD 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __VDPU382_H264D_H__ 18 #define __VDPU382_H264D_H__ 19 20 #include "vdpu382_com.h" 21 22 /* base: OFFSET_CODEC_PARAMS_REGS */ 23 typedef struct Vdpu382RegH264dParam_t { 24 struct SWREG64_H26X_SET { 25 RK_U32 h26x_frame_orslice : 1; 26 RK_U32 h26x_rps_mode : 1; 27 RK_U32 h26x_stream_mode : 1; 28 RK_U32 h26x_stream_lastpacket : 1; 29 RK_U32 h264_firstslice_flag : 1; 30 RK_U32 reserve : 27; 31 } reg64; 32 33 struct SWREG65_CUR_POC { 34 RK_U32 cur_top_poc : 32; 35 } reg65; 36 37 struct SWREG66_H264_CUR_POC1 { 38 RK_U32 cur_bot_poc : 32; 39 } reg66; 40 41 RK_U32 reg67_98_ref_poc[32]; 42 43 struct SWREG99_H264_REG0_3_INFO { 44 45 RK_U32 ref0_field : 1; 46 RK_U32 ref0_topfield_used : 1; 47 RK_U32 ref0_botfield_used : 1; 48 RK_U32 ref0_colmv_use_flag : 1; 49 RK_U32 ref0_reserve : 4; 50 51 RK_U32 ref1_field : 1; 52 RK_U32 ref1_topfield_used : 1; 53 RK_U32 ref1_botfield_used : 1; 54 RK_U32 ref1_colmv_use_flag : 1; 55 RK_U32 ref1_reserve : 4; 56 57 RK_U32 ref2_field : 1; 58 RK_U32 ref2_topfield_used : 1; 59 RK_U32 ref2_botfield_used : 1; 60 RK_U32 ref2_colmv_use_flag : 1; 61 RK_U32 ref2_reserve : 4; 62 63 RK_U32 ref3_field : 1; 64 RK_U32 ref3_topfield_used : 1; 65 RK_U32 ref3_botfield_used : 1; 66 RK_U32 ref3_colmv_use_flag : 1; 67 RK_U32 ref3_reserve : 4; 68 } reg99; 69 70 struct SWREG100_H264_REG4_7_INFO { 71 72 RK_U32 ref4_field : 1; 73 RK_U32 ref4_topfield_used : 1; 74 RK_U32 ref4_botfield_used : 1; 75 RK_U32 ref4_colmv_use_flag : 1; 76 RK_U32 ref4_reserve : 4; 77 78 RK_U32 ref5_field : 1; 79 RK_U32 ref5_topfield_used : 1; 80 RK_U32 ref5_botfield_used : 1; 81 RK_U32 ref5_colmv_use_flag : 1; 82 RK_U32 ref5_reserve : 4; 83 84 RK_U32 ref6_field : 1; 85 RK_U32 ref6_topfield_used : 1; 86 RK_U32 ref6_botfield_used : 1; 87 RK_U32 ref6_colmv_use_flag : 1; 88 RK_U32 ref6_reserve : 4; 89 90 RK_U32 ref7_field : 1; 91 RK_U32 ref7_topfield_used : 1; 92 RK_U32 ref7_botfield_used : 1; 93 RK_U32 ref7_colmv_use_flag : 1; 94 RK_U32 ref7_reserve : 4; 95 } reg100; 96 97 struct SWREG101_H264_REG8_11_INFO { 98 99 RK_U32 ref8_field : 1; 100 RK_U32 ref8_topfield_used : 1; 101 RK_U32 ref8_botfield_used : 1; 102 RK_U32 ref8_colmv_use_flag : 1; 103 RK_U32 ref8_reserve : 4; 104 105 RK_U32 ref9_field : 1; 106 RK_U32 ref9_topfield_used : 1; 107 RK_U32 ref9_botfield_used : 1; 108 RK_U32 ref9_colmv_use_flag : 1; 109 RK_U32 ref9_reserve : 4; 110 111 RK_U32 ref10_field : 1; 112 RK_U32 ref10_topfield_used : 1; 113 RK_U32 ref10_botfield_used : 1; 114 RK_U32 ref10_colmv_use_flag : 1; 115 RK_U32 ref10_reserve : 4; 116 117 RK_U32 ref11_field : 1; 118 RK_U32 ref11_topfield_used : 1; 119 RK_U32 ref11_botfield_used : 1; 120 RK_U32 ref11_colmv_use_flag : 1; 121 RK_U32 ref11_reserve : 4; 122 } reg101; 123 124 struct SWREG102_H264_REG12_15_INFO { 125 126 RK_U32 ref12_field : 1; 127 RK_U32 ref12_topfield_used : 1; 128 RK_U32 ref12_botfield_used : 1; 129 RK_U32 ref12_colmv_use_flag : 1; 130 RK_U32 ref12_reserve : 4; 131 132 RK_U32 ref13_field : 1; 133 RK_U32 ref13_topfield_used : 1; 134 RK_U32 ref13_botfield_used : 1; 135 RK_U32 ref13_colmv_use_flag : 1; 136 RK_U32 ref13_reserve : 4; 137 138 RK_U32 ref14_field : 1; 139 RK_U32 ref14_topfield_used : 1; 140 RK_U32 ref14_botfield_used : 1; 141 RK_U32 ref14_colmv_use_flag : 1; 142 RK_U32 ref14_reserve : 4; 143 144 RK_U32 ref15_field : 1; 145 RK_U32 ref15_topfield_used : 1; 146 RK_U32 ref15_botfield_used : 1; 147 RK_U32 ref15_colmv_use_flag : 1; 148 RK_U32 ref15_reserve : 4; 149 } reg102; 150 151 struct SWREG103_111_NO_USE_REGS { 152 RK_U32 reserve; 153 } no_use_regs[9]; 154 155 struct SWREG112_ERROR_REF_INFO { 156 RK_U32 avs2_ref_error_field : 1; 157 RK_U32 avs2_ref_error_topfield : 1; 158 RK_U32 ref_error_topfield_used : 1; 159 RK_U32 ref_error_botfield_used : 1; 160 RK_U32 reserve : 28; 161 } reg112; 162 } Vdpu382RegH264dParam; 163 164 /* base: OFFSET_CODEC_ADDR_REGS */ 165 typedef struct Vdpu382RegH264dAddr_t { 166 /* SWREG160 */ 167 RK_U32 reg160_no_use; 168 169 /* SWREG161 */ 170 RK_U32 pps_base; 171 172 /* SWREG162 */ 173 RK_U32 reg162_no_use; 174 175 /* SWREG163 */ 176 RK_U32 rps_base; 177 178 /* SWREG164~179 */ 179 RK_U32 ref_base[16]; 180 181 /* SWREG180 */ 182 RK_U32 scanlist_addr; 183 184 /* SWREG181~196 */ 185 RK_U32 colmv_base[16]; 186 187 /* SWREG197 */ 188 RK_U32 cabactbl_base; 189 190 /* SWREG198*/ 191 RK_U32 reg198_scale_down_luma_base; 192 193 /* SWREG199*/ 194 RK_U32 reg199_scale_down_chorme_base; 195 196 } Vdpu382RegH264dAddr; 197 198 typedef struct Vdpu382H264dHighPoc_t { 199 /* SWREG200 */ 200 struct SWREG200_REF0_7_POC_HIGHBIT { 201 RK_U32 ref0_poc_highbit : 4; 202 RK_U32 ref1_poc_highbit : 4; 203 RK_U32 ref2_poc_highbit : 4; 204 RK_U32 ref3_poc_highbit : 4; 205 RK_U32 ref4_poc_highbit : 4; 206 RK_U32 ref5_poc_highbit : 4; 207 RK_U32 ref6_poc_highbit : 4; 208 RK_U32 ref7_poc_highbit : 4; 209 } reg200; 210 struct SWREG201_REF8_15_POC_HIGHBIT { 211 RK_U32 ref8_poc_highbit : 4; 212 RK_U32 ref9_poc_highbit : 4; 213 RK_U32 ref10_poc_highbit : 4; 214 RK_U32 ref11_poc_highbit : 4; 215 RK_U32 ref12_poc_highbit : 4; 216 RK_U32 ref13_poc_highbit : 4; 217 RK_U32 ref14_poc_highbit : 4; 218 RK_U32 ref15_poc_highbit : 4; 219 } reg201; 220 struct SWREG200_REF16_23_POC_HIGHBIT { 221 RK_U32 ref16_poc_highbit : 4; 222 RK_U32 ref17_poc_highbit : 4; 223 RK_U32 ref18_poc_highbit : 4; 224 RK_U32 ref19_poc_highbit : 4; 225 RK_U32 ref20_poc_highbit : 4; 226 RK_U32 ref21_poc_highbit : 4; 227 RK_U32 ref22_poc_highbit : 4; 228 RK_U32 ref23_poc_highbit : 4; 229 } reg202; 230 struct SWREG200_REF24_31_POC_HIGHBIT { 231 RK_U32 ref24_poc_highbit : 4; 232 RK_U32 ref25_poc_highbit : 4; 233 RK_U32 ref26_poc_highbit : 4; 234 RK_U32 ref27_poc_highbit : 4; 235 RK_U32 ref28_poc_highbit : 4; 236 RK_U32 ref29_poc_highbit : 4; 237 RK_U32 ref30_poc_highbit : 4; 238 RK_U32 ref31_poc_highbit : 4; 239 } reg203; 240 struct SWREG200_CUR_POC_HIGHBIT { 241 RK_U32 cur_poc_highbit : 4; 242 RK_U32 reserver : 28; 243 } reg204; 244 245 struct SWREG205_DEBUG_INFO { 246 RK_U32 force_softreset_valid : 1; 247 RK_U32 force_mmureset_valid : 1; 248 RK_U32 reserve0 : 2; 249 RK_U32 error_auto_rst_disable : 1; 250 RK_U32 right_auto_rst_disable : 1; 251 RK_U32 buf_empty_security_en : 1; 252 RK_U32 coord_realtime_report_en : 1; 253 254 RK_U32 fetchcmd_merge_dis : 1; 255 RK_U32 dec_timeout_dis : 1; 256 RK_U32 reg_cfg_wr_dis : 1; 257 RK_U32 reserve1 : 1; 258 RK_U32 force_busidle_req : 1; 259 RK_U32 mmu_force_busidle_req : 1; 260 RK_U32 mmu_sel : 1; 261 RK_U32 reserve2 : 17; 262 263 } reg205; 264 } Vdpu382H264dHighPoc_t; 265 266 typedef struct Vdpu382H264dRegSet_t { 267 Vdpu382RegCommon common; 268 Vdpu382RegH264dParam h264d_param; 269 Vdpu382RegCommonAddr common_addr; 270 Vdpu382RegH264dAddr h264d_addr; 271 Vdpu382H264dHighPoc_t h264d_highpoc; 272 Vdpu382RegIrqStatus irq_status; 273 Vdpu382RegStatistic statistic; 274 } Vdpu382H264dRegSet; 275 276 #endif /* __VDPU382_H264D_H__ */ 277