1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Rockchip VAD Preprocess 4 * 5 * Copyright (C) 2018 Fuzhou Rockchip Electronics Co., Ltd 6 * 7 */ 8 9 .arch armv8-a 10 .file "vad_preprocess_arm64.S" 11 .text 12 .align 2 13 .global vad_preprocess_init 14 .type vad_preprocess_init, %function 15vad_preprocess_init: 16 adrp x2, .LANCHOR0 17 add x1, x2, :lo12:.LANCHOR0 18 ldr w3, [x0, 8] 19 strh w3, [x2, #:lo12:.LANCHOR0] 20 ldr w2, [x0, 4] 21 strh w2, [x1, 2] 22 ldr w2, [x0, 12] 23 strh w2, [x1, 4] 24 ldr w2, [x0] 25 strh w2, [x1, 6] 26 ldr w2, [x0, 16] 27 and w0, w2, 511 28 tbz x2, 9, .L2 29 mvn w0, w0 30.L2: 31 strh w0, [x1, 8] 32 ret 33 .size vad_preprocess_init, .-vad_preprocess_init 34 .align 2 35 .global vad_preprocess 36 .type vad_preprocess, %function 37vad_preprocess: 38 adrp x4, .LANCHOR0 39 add x2, x4, :lo12:.LANCHOR0 40 mov w8, 15349 41 ldrsh w1, [x2, 8] 42 ldrsh w7, [x2, 10] 43 ldrsh w6, [x2, 12] 44 ldrsh w3, [x2, 16] 45 mul w0, w1, w0 46 mov w1, 32 47 sdiv w0, w0, w1 48 ldrsh w1, [x2, 14] 49 mov w2, -30697 50 mul w2, w7, w2 51 mul w5, w0, w8 52 sxtw x2, w2 53 add x2, x2, w5, sxtw 54 smaddl x3, w3, w8, x2 55 mov w2, -30632 56 smsubl x2, w6, w2, x3 57 mov w3, 14379 58 smsubl x1, w1, w3, x2 59 cmp x1, 0 60 ble .L5 61 add x1, x1, 8192 62 asr x1, x1, 14 63.L6: 64 add x2, x4, :lo12:.LANCHOR0 65 sxth w1, w1 66 cmp w1, 0 67 ldrh w3, [x2, 18] 68 strh w0, [x2, 10] 69 add w3, w3, 1 70 ldr w0, [x2, 20] 71 sxth w3, w3 72 strh w1, [x2, 12] 73 csneg w1, w1, w1, ge 74 strh w3, [x2, 18] 75 negs w5, w3 76 add w0, w1, w0 77 strh w7, [x2, 16] 78 and w3, w3, 255 79 strh w6, [x2, 14] 80 and w5, w5, 255 81 str w0, [x2, 20] 82 csneg w3, w3, w5, mi 83 cbnz w3, .L7 84 ldr w3, [x2, 24] 85 cmp w3, 99 86 bgt .L8 87 add w0, w0, 128 88 mov w5, 256 89 add x2, x2, 32 90 sdiv w0, w0, w5 91 strh w0, [x2, w3, sxtw 1] 92.L9: 93 add x2, x4, :lo12:.LANCHOR0 94 cmp w3, 99 95 ldrsh w0, [x2, 32] 96 bgt .L11 97 add x2, x2, 32 98 mov x5, 0 99.L12: 100 add x5, x5, 1 101 cmp w3, w5 102 bgt .L13 103.L14: 104 add x2, x4, :lo12:.LANCHOR0 105 mov w6, 230 106 add w3, w3, 1 107 ldrsh w5, [x2, 6] 108 strh wzr, [x2, 18] 109 stp wzr, w3, [x2, 20] 110 mul w5, w5, w6 111 mov w6, 26 112 add w5, w5, 128 113 madd w0, w0, w6, w5 114 mov w5, 256 115 sdiv w0, w0, w5 116 strh w0, [x2, 6] 117.L7: 118 add x0, x4, :lo12:.LANCHOR0 119 ldrsh w3, [x4, #:lo12:.LANCHOR0] 120 ldrsh w2, [x0, 6] 121 ldrsh w5, [x0, 2] 122 madd w2, w2, w5, w3 123 cmp w1, w2 124 ble .L16 125 ldrh w1, [x0, 432] 126 add w1, w1, 1 127 sxth w1, w1 128 strh w1, [x0, 432] 129 ldrsh w0, [x0, 4] 130 cmp w0, w1 131 cset w0, lt 132 ret 133.L5: 134 sub x1, x1, #8192 135 mov x2, 16384 136 sdiv x1, x1, x2 137 b .L6 138.L8: 139 add x5, x2, 34 140 add x2, x2, 232 141.L10: 142 ldrh w6, [x5] 143 add x5, x5, 2 144 strh w6, [x5, -4] 145 cmp x2, x5 146 bne .L10 147 add w0, w0, 128 148 mov w5, 256 149 add x2, x4, :lo12:.LANCHOR0 150 sdiv w0, w0, w5 151 strh w0, [x2, 230] 152 b .L9 153.L13: 154 lsl x6, x5, 1 155 ldrsh w7, [x6, x2] 156 ldrh w6, [x6, x2] 157 cmp w7, w0 158 csel w0, w6, w0, le 159 sxth w0, w0 160 b .L12 161.L11: 162 add x5, x2, 34 163 add x2, x2, 232 164.L15: 165 ldrsh w7, [x5] 166 ldrh w6, [x5], 2 167 cmp w7, w0 168 csel w0, w6, w0, le 169 cmp x2, x5 170 sxth w0, w0 171 bne .L15 172 b .L14 173.L16: 174 strh wzr, [x0, 432] 175 mov w0, 0 176 ret 177 .size vad_preprocess, .-vad_preprocess 178 .align 2 179 .global vad_preprocess_destroy 180 .type vad_preprocess_destroy, %function 181vad_preprocess_destroy: 182 adrp x0, .LANCHOR0 183 add x0, x0, :lo12:.LANCHOR0 184 add x2, x0, 32 185 mov x1, 0 186 strh wzr, [x0, 10] 187 strh wzr, [x0, 16] 188 strh wzr, [x0, 12] 189 strh wzr, [x0, 14] 190 strh wzr, [x0, 18] 191 strh wzr, [x0, 432] 192.L21: 193 strh wzr, [x1, x2] 194 add x1, x1, 2 195 cmp x1, 200 196 bne .L21 197 mov w1, 32 198 strh wzr, [x0, 6] 199 strh w1, [x0, 8] 200 stp wzr, wzr, [x0, 20] 201 ret 202 .size vad_preprocess_destroy, .-vad_preprocess_destroy 203 .align 2 204 .global vad_preprocess_update_params 205 .type vad_preprocess_update_params, %function 206vad_preprocess_update_params: 207 adrp x1, .LANCHOR0+6 208 ldrsh w1, [x1, #:lo12:.LANCHOR0+6] 209 str w1, [x0] 210 ret 211 .size vad_preprocess_update_params, .-vad_preprocess_update_params 212 .bss 213 .align 3 214 .set .LANCHOR0,. + 0 215 .type g_sound_thd, %object 216 .size g_sound_thd, 2 217g_sound_thd: 218 .zero 2 219 .type g_noise_level, %object 220 .size g_noise_level, 2 221g_noise_level: 222 .zero 2 223 .type g_vad_con_thd, %object 224 .size g_vad_con_thd, 2 225g_vad_con_thd: 226 .zero 2 227 .type g_noise_abs, %object 228 .size g_noise_abs, 2 229g_noise_abs: 230 .zero 2 231 .type g_signal_gain, %object 232 .size g_signal_gain, 2 233g_signal_gain: 234 .zero 2 235 .type g_xn_1, %object 236 .size g_xn_1, 2 237g_xn_1: 238 .zero 2 239 .type g_yn_1, %object 240 .size g_yn_1, 2 241g_yn_1: 242 .zero 2 243 .type g_yn_2, %object 244 .size g_yn_2, 2 245g_yn_2: 246 .zero 2 247 .type g_xn_2, %object 248 .size g_xn_2, 2 249g_xn_2: 250 .zero 2 251 .type g_sample_cnt, %object 252 .size g_sample_cnt, 2 253g_sample_cnt: 254 .zero 2 255 .type g_sum_abs_frm, %object 256 .size g_sum_abs_frm, 4 257g_sum_abs_frm: 258 .zero 4 259 .type frm_count, %object 260 .size frm_count, 4 261frm_count: 262 .zero 4 263 .zero 4 264 .type g_ave_abs_rec, %object 265 .size g_ave_abs_rec, 400 266g_ave_abs_rec: 267 .zero 400 268 .type g_vad_cnt, %object 269 .size g_vad_cnt, 2 270g_vad_cnt: 271 .zero 2 272 .ident "GCC: (Linaro GCC 6.3-2017.05) 6.3.1 20170404" 273 .section .note.GNU-stack,"",@progbits 274