1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * 4 * (C) COPYRIGHT 2019-2022 ARM Limited. All rights reserved. 5 * 6 * This program is free software and is provided to you under the terms of the 7 * GNU General Public License version 2 as published by the Free Software 8 * Foundation, and any use by you of this program is subject to the terms 9 * of such GNU license. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, you can access it online at 18 * http://www.gnu.org/licenses/gpl-2.0.html. 19 * 20 */ 21 22 #ifndef _UAPI_KBASE_GPU_REGMAP_H_ 23 #define _UAPI_KBASE_GPU_REGMAP_H_ 24 25 #if MALI_USE_CSF 26 #include "backend/mali_kbase_gpu_regmap_csf.h" 27 #else 28 #include "backend/mali_kbase_gpu_regmap_jm.h" 29 #endif /* !MALI_USE_CSF */ 30 31 /* Begin Register Offsets */ 32 /* GPU control registers */ 33 34 #define GPU_CONTROL_BASE 0x0000 35 #define GPU_CONTROL_REG(r) (GPU_CONTROL_BASE + (r)) 36 37 #define GPU_ID 0x000 /* (RO) GPU and revision identifier */ 38 39 #define GPU_IRQ_CLEAR 0x024 /* (WO) */ 40 #define GPU_IRQ_STATUS 0x02C /* (RO) */ 41 42 #define SHADER_READY_LO 0x140 /* (RO) Shader core ready bitmap, low word */ 43 #define SHADER_READY_HI 0x144 /* (RO) Shader core ready bitmap, high word */ 44 45 #define TILER_READY_LO 0x150 /* (RO) Tiler core ready bitmap, low word */ 46 #define TILER_READY_HI 0x154 /* (RO) Tiler core ready bitmap, high word */ 47 48 #define L2_READY_LO 0x160 /* (RO) Level 2 cache ready bitmap, low word */ 49 #define L2_READY_HI 0x164 /* (RO) Level 2 cache ready bitmap, high word */ 50 51 #define SHADER_PWRON_LO 0x180 /* (WO) Shader core power on bitmap, low word */ 52 #define SHADER_PWRON_HI 0x184 /* (WO) Shader core power on bitmap, high word */ 53 54 #define TILER_PWRON_LO 0x190 /* (WO) Tiler core power on bitmap, low word */ 55 #define TILER_PWRON_HI 0x194 /* (WO) Tiler core power on bitmap, high word */ 56 57 #define L2_PWRON_LO 0x1A0 /* (WO) Level 2 cache power on bitmap, low word */ 58 #define L2_PWRON_HI 0x1A4 /* (WO) Level 2 cache power on bitmap, high word */ 59 60 /* Job control registers */ 61 62 #define JOB_CONTROL_BASE 0x1000 63 64 #define JOB_CONTROL_REG(r) (JOB_CONTROL_BASE + (r)) 65 66 #define JOB_IRQ_CLEAR 0x004 /* Interrupt clear register */ 67 #define JOB_IRQ_MASK 0x008 /* Interrupt mask register */ 68 #define JOB_IRQ_STATUS 0x00C /* Interrupt status register */ 69 70 /* MMU control registers */ 71 72 #define MEMORY_MANAGEMENT_BASE 0x2000 73 74 #define MMU_REG(r) (MEMORY_MANAGEMENT_BASE + (r)) 75 76 #define MMU_IRQ_RAWSTAT 0x000 /* (RW) Raw interrupt status register */ 77 #define MMU_IRQ_CLEAR 0x004 /* (WO) Interrupt clear register */ 78 #define MMU_IRQ_MASK 0x008 /* (RW) Interrupt mask register */ 79 #define MMU_IRQ_STATUS 0x00C /* (RO) Interrupt status register */ 80 81 #define MMU_AS0 0x400 /* Configuration registers for address space 0 */ 82 83 /* MMU address space control registers */ 84 85 #define MMU_AS_REG(n, r) (MMU_REG(MMU_AS0 + ((n) << 6)) + (r)) 86 87 #define AS_TRANSTAB_LO 0x00 /* (RW) Translation Table Base Address for address space n, low word */ 88 #define AS_TRANSTAB_HI 0x04 /* (RW) Translation Table Base Address for address space n, high word */ 89 #define AS_MEMATTR_LO 0x08 /* (RW) Memory attributes for address space n, low word. */ 90 #define AS_MEMATTR_HI 0x0C /* (RW) Memory attributes for address space n, high word. */ 91 #define AS_COMMAND 0x18 /* (WO) MMU command register for address space n */ 92 93 /* (RW) Translation table configuration for address space n, low word */ 94 #define AS_TRANSCFG_LO 0x30 95 /* (RW) Translation table configuration for address space n, high word */ 96 #define AS_TRANSCFG_HI 0x34 97 98 #endif /* _UAPI_KBASE_GPU_REGMAP_H_ */ 99