1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Techpoint Lib 4 * 5 * Copyright (C) 2023 Rockchip Electronics Co., Ltd. 6 */ 7 8 #ifndef _TECHPOINT_COMMON_H 9 #define _TECHPOINT_COMMON_H 10 11 #include <linux/clk.h> 12 #include <linux/device.h> 13 #include <linux/delay.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/i2c.h> 16 #include <linux/module.h> 17 #include <linux/pm_runtime.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/sysfs.h> 20 #include <linux/slab.h> 21 #include <linux/version.h> 22 #include <linux/rk-camera-module.h> 23 #include <media/media-entity.h> 24 #include <media/v4l2-async.h> 25 #include <media/v4l2-ctrls.h> 26 #include <media/v4l2-subdev.h> 27 #include <linux/pinctrl/consumer.h> 28 #include <linux/rk-preisp.h> 29 #include <linux/sched.h> 30 #include <linux/kthread.h> 31 #include <linux/of.h> 32 #include <linux/of_graph.h> 33 34 #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x0) 35 36 #define TECHPOINT_CAMERA_XVCLK_FREQ "xvclk_freq" 37 38 #define TECHPOINT_TEST_PATTERN 0 39 #define DEF_1080P 1 40 #define TECHPOINT_SHARING_POWER 1 41 42 #define INPUT_STATUS_REG 0x01 43 #define PAGE_REG 0x40 44 #define CHIP_ID_H_REG 0xFE 45 #define CHIP_ID_L_REG 0xFF 46 47 #define INPUT_STATUS_MASK 0x80 48 49 enum techpoint_chips { 50 CHIP_UNKNOWN = 0, 51 CHIP_TP2855, 52 CHIP_TP2815, 53 CHIP_TP9930, 54 CHIP_TP9950, 55 }; 56 57 enum techpoint_input_type { 58 TECHPOINT_MIPI = 0, 59 TECHPOINT_DVP_BT1120, 60 TECHPOINT_DVP_BT565, 61 }; 62 63 enum techpoint_support_reso { 64 TECHPOINT_S_RESO_720P_25 = 0, 65 TECHPOINT_S_RESO_1080P_25, 66 TECHPOINT_S_RESO_720P_30, 67 TECHPOINT_S_RESO_1080P_30, 68 TECHPOINT_S_RESO_SD, 69 TECHPOINT_S_RESO_PAL, 70 TECHPOINT_S_RESO_NTSC, 71 TECHPOINT_S_RESO_NUMS, 72 }; 73 74 struct techpoint_video_modes { 75 u32 bus_fmt; 76 u32 width; 77 u32 height; 78 struct v4l2_fract max_fps; 79 u32 bpp; 80 u32 lane; 81 s64 link_freq_value; 82 u32 vc[PAD_MAX]; 83 const struct regval *common_reg_list; 84 int common_reg_size; 85 enum techpoint_support_reso channel_reso[PAD_MAX]; 86 }; 87 88 /* Audio output port formats */ 89 enum techpoint_audfmts { 90 AUDFMT_I2S = 0, 91 AUDFMT_DSP, 92 }; 93 94 struct techpoint_audio { 95 enum techpoint_audfmts audfmt; 96 int mclk_fs; 97 int cascade_num; 98 int cascade_order; 99 int slave_num; 100 struct techpoint *slave_tp[3]; 101 }; 102 103 struct techpoint { 104 struct device dev; 105 struct i2c_client *client; 106 struct clk *xvclk; 107 struct gpio_desc *reset_gpio; 108 struct gpio_desc *power_gpio; 109 struct pinctrl *pinctrl; 110 struct pinctrl_state *pins_sleep; 111 struct pinctrl_state *pins_default; 112 struct media_pad pad[PAD_MAX]; 113 struct v4l2_subdev subdev; 114 struct v4l2_ctrl *pixel_rate_ctrl; 115 struct v4l2_ctrl *link_freq_ctrl; 116 struct v4l2_ctrl_handler ctrl_handler; 117 struct mutex mutex; 118 struct regulator_bulk_data *supplies; 119 u32 xvclk_freq_value; 120 struct techpoint_audio *audio_in; 121 struct techpoint_audio *audio_out; 122 int i2c_idx; 123 u32 data_lanes; 124 125 enum techpoint_chips chip_id; 126 struct techpoint_video_modes *video_modes; 127 struct techpoint_video_modes *cur_video_mode; 128 u32 video_modes_num; 129 enum techpoint_input_type input_type; 130 131 u32 module_index; 132 const char *module_facing; 133 const char *module_name; 134 const char *len_name; 135 bool power_on; 136 bool streaming; 137 bool do_reset; 138 139 u8 detect_status[PAD_MAX]; 140 struct task_struct *detect_thread; 141 }; 142 143 #endif // _TECHPOINT_COMMON_H 144