1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2017-2026, STMicroelectronics - All Rights Reserved 4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. 5 */ 6/dts-v1/; 7 8#include "stm32mp157.dtsi" 9#include "stm32mp15xc.dtsi" 10#include "stm32mp15-pinctrl.dtsi" 11#include "stm32mp15xxaa-pinctrl.dtsi" 12#include <dt-bindings/clock/stm32mp1-clksrc.h> 13#include "stm32mp15-ddr3-2x4Gb-1066-binG.dtsi" 14 15/ { 16 model = "STMicroelectronics STM32MP157C eval daughter"; 17 compatible = "st,stm32mp157c-ed1", "st,stm32mp157"; 18 19 aliases { 20 serial0 = &uart4; 21 }; 22 23 chosen { 24 stdout-path = "serial0:115200n8"; 25 }; 26 27 memory@c0000000 { 28 device_type = "memory"; 29 reg = <0xC0000000 0x40000000>; 30 }; 31}; 32 33&bsec { 34 board_id: board-id@ec { 35 reg = <0xec 0x4>; 36 st,non-secure-otp; 37 }; 38}; 39 40&clk_hse { 41 st,digbypass; 42}; 43 44&cpu0 { 45 cpu-supply = <&vddcore>; 46}; 47 48&cpu1 { 49 cpu-supply = <&vddcore>; 50}; 51 52&cryp1 { 53 status = "okay"; 54}; 55 56&ddr { 57 vdd-supply = <&vdd_ddr>; 58 vtt-supply = <&vtt_ddr>; 59 vref-supply = <&vref_ddr>; 60}; 61 62&hash1 { 63 status = "okay"; 64}; 65 66&i2c4 { 67 pinctrl-names = "default"; 68 pinctrl-0 = <&i2c4_pins_a>; 69 i2c-scl-rising-time-ns = <185>; 70 i2c-scl-falling-time-ns = <20>; 71 clock-frequency = <400000>; 72 status = "okay"; 73 74 pmic: stpmic@33 { 75 compatible = "st,stpmic1"; 76 reg = <0x33>; 77 interrupts-extended = <&exti_pwr 55 IRQ_TYPE_EDGE_FALLING>; 78 interrupt-controller; 79 #interrupt-cells = <2>; 80 status = "okay"; 81 82 regulators { 83 compatible = "st,stpmic1-regulators"; 84 ldo1-supply = <&v3v3>; 85 ldo2-supply = <&v3v3>; 86 ldo3-supply = <&vdd_ddr>; 87 ldo5-supply = <&v3v3>; 88 ldo6-supply = <&v3v3>; 89 pwr_sw1-supply = <&bst_out>; 90 pwr_sw2-supply = <&bst_out>; 91 92 vddcore: buck1 { 93 regulator-name = "vddcore"; 94 regulator-min-microvolt = <1200000>; 95 regulator-max-microvolt = <1350000>; 96 regulator-always-on; 97 regulator-initial-mode = <0>; 98 regulator-over-current-protection; 99 }; 100 101 vdd_ddr: buck2 { 102 regulator-name = "vdd_ddr"; 103 regulator-min-microvolt = <1350000>; 104 regulator-max-microvolt = <1350000>; 105 regulator-always-on; 106 regulator-initial-mode = <0>; 107 regulator-over-current-protection; 108 }; 109 110 vdd: buck3 { 111 regulator-name = "vdd"; 112 regulator-min-microvolt = <3300000>; 113 regulator-max-microvolt = <3300000>; 114 regulator-always-on; 115 st,mask-reset; 116 regulator-initial-mode = <0>; 117 regulator-over-current-protection; 118 }; 119 120 v3v3: buck4 { 121 regulator-name = "v3v3"; 122 regulator-min-microvolt = <3300000>; 123 regulator-max-microvolt = <3300000>; 124 regulator-always-on; 125 regulator-over-current-protection; 126 regulator-initial-mode = <0>; 127 }; 128 129 vdda: ldo1 { 130 regulator-name = "vdda"; 131 regulator-min-microvolt = <2900000>; 132 regulator-max-microvolt = <2900000>; 133 }; 134 135 v2v8: ldo2 { 136 regulator-name = "v2v8"; 137 regulator-min-microvolt = <2800000>; 138 regulator-max-microvolt = <2800000>; 139 }; 140 141 vtt_ddr: ldo3 { 142 regulator-name = "vtt_ddr"; 143 regulator-always-on; 144 regulator-over-current-protection; 145 st,regulator-sink-source; 146 }; 147 148 vdd_usb: ldo4 { 149 regulator-name = "vdd_usb"; 150 regulator-min-microvolt = <3300000>; 151 regulator-max-microvolt = <3300000>; 152 }; 153 154 vdd_sd: ldo5 { 155 regulator-name = "vdd_sd"; 156 regulator-min-microvolt = <2900000>; 157 regulator-max-microvolt = <2900000>; 158 regulator-boot-on; 159 }; 160 161 v1v8: ldo6 { 162 regulator-name = "v1v8"; 163 regulator-min-microvolt = <1800000>; 164 regulator-max-microvolt = <1800000>; 165 }; 166 167 vref_ddr: vref_ddr { 168 regulator-name = "vref_ddr"; 169 regulator-always-on; 170 }; 171 172 bst_out: boost { 173 regulator-name = "bst_out"; 174 }; 175 176 vbus_otg: pwr_sw1 { 177 regulator-name = "vbus_otg"; 178 }; 179 180 vbus_sw: pwr_sw2 { 181 regulator-name = "vbus_sw"; 182 regulator-active-discharge = <1>; 183 }; 184 }; 185 }; 186}; 187 188&iwdg2 { 189 timeout-sec = <32>; 190 status = "okay"; 191}; 192 193&pwr_regulators { 194 vdd-supply = <&vdd>; 195 vdd_3v3_usbfs-supply = <&vdd_usb>; 196}; 197 198&rcc { 199 st,clksrc = < 200 CLK_MPU_PLL1P 201 CLK_AXI_PLL2P 202 CLK_MCU_PLL3P 203 CLK_RTC_LSE 204 CLK_CKPER_HSE 205 CLK_FMC_ACLK 206 CLK_QSPI_ACLK 207 CLK_SDMMC12_PLL4P 208 CLK_STGEN_HSE 209 CLK_I2C46_HSI 210 CLK_UART24_HSI 211 >; 212 213 st,clkdiv = < 214 DIV(DIV_MPU, 1) 215 DIV(DIV_AXI, 0) 216 DIV(DIV_MCU, 0) 217 DIV(DIV_APB1, 1) 218 DIV(DIV_APB2, 1) 219 DIV(DIV_APB3, 1) 220 DIV(DIV_APB4, 1) 221 DIV(DIV_APB5, 2) 222 DIV(DIV_RTC, 23) 223 >; 224 225 st,pll_vco { 226 pll2_vco_1066Mhz: pll2-vco-1066Mhz { 227 src = <CLK_PLL12_HSE>; 228 divmn = <2 65>; 229 frac = <0x1400>; 230 }; 231 232 pll3_vco_417Mhz: pll3-vco-417Mhz { 233 src = <CLK_PLL3_HSE>; 234 divmn = <1 33>; 235 frac = <0x1a04>; 236 }; 237 238 pll4_vco_594Mhz: pll4-vco-594Mhz { 239 src = <CLK_PLL4_HSE>; 240 divmn = <3 98>; 241 }; 242 }; 243 244 /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ 245 pll2: st,pll@1 { 246 compatible = "st,stm32mp1-pll"; 247 reg = <1>; 248 249 st,pll = <&pll2_cfg1>; 250 251 pll2_cfg1: pll2_cfg1 { 252 st,pll_vco = <&pll2_vco_1066Mhz>; 253 st,pll_div_pqr = <1 0 0>; 254 }; 255 }; 256 257 /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ 258 pll3: st,pll@2 { 259 compatible = "st,stm32mp1-pll"; 260 reg = <2>; 261 262 st,pll = <&pll3_cfg1>; 263 264 pll3_cfg1: pll3_cfg1 { 265 st,pll_vco = <&pll3_vco_417Mhz>; 266 st,pll_div_pqr = <1 16 36>; 267 }; 268 }; 269 270 /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ 271 pll4: st,pll@3 { 272 compatible = "st,stm32mp1-pll"; 273 reg = <3>; 274 275 st,pll = <&pll4_cfg1>; 276 277 pll4_cfg1: pll4_cfg1 { 278 st,pll_vco = <&pll4_vco_594Mhz>; 279 st,pll_div_pqr = <5 7 7>; 280 }; 281 }; 282}; 283 284&rng1 { 285 status = "okay"; 286}; 287 288&rtc { 289 status = "okay"; 290}; 291 292&sdmmc1 { 293 pinctrl-names = "default"; 294 pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; 295 disable-wp; 296 st,sig-dir; 297 st,neg-edge; 298 st,use-ckin; 299 bus-width = <4>; 300 vmmc-supply = <&vdd_sd>; 301 sd-uhs-sdr12; 302 sd-uhs-sdr25; 303 sd-uhs-sdr50; 304 sd-uhs-ddr50; 305 status = "okay"; 306}; 307 308&sdmmc2 { 309 pinctrl-names = "default"; 310 pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_a>; 311 non-removable; 312 no-sd; 313 no-sdio; 314 st,neg-edge; 315 bus-width = <8>; 316 vmmc-supply = <&v3v3>; 317 vqmmc-supply = <&vdd>; 318 mmc-ddr-3_3v; 319 status = "okay"; 320}; 321 322&uart4 { 323 pinctrl-names = "default"; 324 pinctrl-0 = <&uart4_pins_a>; 325 status = "okay"; 326}; 327