1 // SPDX-License-Identifier: BSD-2-Clause
2 /*
3 * Copyright (c) 2021-2024, STMicroelectronics
4 */
5
6 #include <assert.h>
7 #include <drivers/clk.h>
8 #include <drivers/clk_dt.h>
9 #include <drivers/firewall.h>
10 #include <drivers/stm32_rif.h>
11 #include <drivers/stm32_risaf.h>
12 #include <dt-bindings/firewall/stm32mp25-risaf.h>
13 #include <io.h>
14 #include <kernel/boot.h>
15 #include <kernel/dt.h>
16 #include <kernel/pm.h>
17 #include <kernel/spinlock.h>
18 #include <kernel/tee_misc.h>
19 #include <libfdt.h>
20 #include <mm/core_memprot.h>
21 #include <platform_config.h>
22 #include <stdint.h>
23 #include <util.h>
24
25 /* RISAF general registers (base relative) */
26 #define _RISAF_CR U(0x00)
27 #define _RISAF_SR U(0x04)
28 #define _RISAF_IASR U(0x08)
29 #define _RISAF_IACR U(0xC)
30 #define _RISAF_IAESR0 U(0x20)
31 #define _RISAF_IADDR0 U(0x24)
32 #define _RISAF_IAESR1 U(0x28)
33 #define _RISAF_IADDR1 U(0x2C)
34 #define _RISAF_KEYR U(0x30)
35 #define _RISAF_HWCFGR U(0xFF0)
36 #define _RISAF_VERR U(0xFF4)
37 #define _RISAF_IPIDR U(0xFF8)
38 #define _RISAF_SIDR U(0xFFC)
39
40 /* RISAF general register field description */
41 /* _RISAF_CR register fields */
42 #define _RISAF_CR_GLOCK BIT(0)
43 /* _RISAF_SR register fields */
44 #define _RISAF_SR_KEYVALID BIT(0)
45 #define _RISAF_SR_KEYRDY BIT(1)
46 #define _RISAF_SR_ENCDIS BIT(2)
47 /* _RISAF_IACR register fields */
48 #define _RISAF_IACR_CAEF BIT(0)
49 #define _RISAF_IACR_IAEF0 BIT(1)
50 #define _RISAF_IACR_IAEF1 BIT(2)
51 /* _RISAF_HWCFGR register fields */
52 #define _RISAF_HWCFGR_CFG1_SHIFT U(0)
53 #define _RISAF_HWCFGR_CFG1_MASK GENMASK_32(7, 0)
54 #define _RISAF_HWCFGR_CFG2_SHIFT U(8)
55 #define _RISAF_HWCFGR_CFG2_MASK GENMASK_32(15, 8)
56 #define _RISAF_HWCFGR_CFG3_SHIFT U(16)
57 #define _RISAF_HWCFGR_CFG3_MASK GENMASK_32(23, 16)
58 #define _RISAF_HWCFGR_CFG4_SHIFT U(24)
59 #define _RISAF_HWCFGR_CFG4_MASK GENMASK_32(31, 24)
60 /* _RISAF_VERR register fields */
61 #define _RISAF_VERR_MINREV_SHIFT U(0)
62 #define _RISAF_VERR_MINREV_MASK GENMASK_32(3, 0)
63 #define _RISAF_VERR_MAJREV_SHIFT U(4)
64 #define _RISAF_VERR_MAJREV_MASK GENMASK_32(7, 4)
65
66 /* RISAF region registers (base relative) */
67 #define _RISAF_REG_BASE U(0x40)
68 #define _RISAF_REG_SIZE U(0x40)
69 #define _RISAF_REG(n) (_RISAF_REG_BASE + \
70 (((n) - 1) * _RISAF_REG_SIZE))
71 #define _RISAF_REG_CFGR_OFFSET U(0x0)
72 #define _RISAF_REG_CFGR(n) (_RISAF_REG(n) + _RISAF_REG_CFGR_OFFSET)
73 #define _RISAF_REG_STARTR_OFFSET U(0x4)
74 #define _RISAF_REG_STARTR(n) (_RISAF_REG(n) + \
75 _RISAF_REG_STARTR_OFFSET)
76 #define _RISAF_REG_ENDR_OFFSET U(0x8)
77 #define _RISAF_REG_ENDR(n) (_RISAF_REG(n) + _RISAF_REG_ENDR_OFFSET)
78 #define _RISAF_REG_CIDCFGR_OFFSET U(0xC)
79 #define _RISAF_REG_CIDCFGR(n) (_RISAF_REG(n) + \
80 _RISAF_REG_CIDCFGR_OFFSET)
81
82 /* RISAF region register field description */
83 /* _RISAF_REG_CFGR(n) register fields */
84 #define _RISAF_REG_CFGR_BREN_SHIFT U(0)
85 #define _RISAF_REG_CFGR_BREN BIT(_RISAF_REG_CFGR_BREN_SHIFT)
86 #define _RISAF_REG_CFGR_SEC_SHIFT U(8)
87 #define _RISAF_REG_CFGR_SEC BIT(_RISAF_REG_CFGR_SEC_SHIFT)
88 #define _RISAF_REG_CFGR_ENC_SHIFT U(15)
89 #define _RISAF_REG_CFGR_ENC BIT(_RISAF_REG_CFGR_ENC_SHIFT)
90 #define _RISAF_REG_CFGR_PRIVC_SHIFT U(16)
91 #define _RISAF_REG_CFGR_PRIVC_MASK GENMASK_32(23, 16)
92 #define _RISAF_REG_CFGR_ALL_MASK (_RISAF_REG_CFGR_BREN | \
93 _RISAF_REG_CFGR_SEC | \
94 _RISAF_REG_CFGR_ENC | \
95 _RISAF_REG_CFGR_PRIVC_MASK)
96
97 /* _RISAF_REG_CIDCFGR(n) register fields */
98 #define _RISAF_REG_CIDCFGR_RDENC_SHIFT U(0)
99 #define _RISAF_REG_CIDCFGR_RDENC_MASK GENMASK_32(7, 0)
100 #define _RISAF_REG_CIDCFGR_WRENC_SHIFT U(16)
101 #define _RISAF_REG_CIDCFGR_WRENC_MASK GENMASK_32(23, 16)
102 #define _RISAF_REG_CIDCFGR_ALL_MASK (_RISAF_REG_CIDCFGR_RDENC_MASK | \
103 _RISAF_REG_CIDCFGR_WRENC_MASK)
104 #define _RISAF_REG_READ_OK(reg, cid) \
105 ((reg) & BIT((cid) + _RISAF_REG_CIDCFGR_RDENC_SHIFT))
106 #define _RISAF_REG_WRITE_OK(reg, cid) \
107 ((reg) & BIT((cid) + _RISAF_REG_CIDCFGR_WRENC_SHIFT))
108
109 #define _RISAF_GET_REGION_ID(cfg) ((cfg) & DT_RISAF_REG_ID_MASK)
110
111 #define _RISAF_NB_CID_SUPPORTED U(8)
112
113 /**
114 * struct stm32_risaf_region - RISAF memory region
115 *
116 * @addr: Region base address.
117 * @len: Length of the memory region.
118 * @cfg: Region configuration.
119 */
120 struct stm32_risaf_region {
121 paddr_t addr;
122 size_t len;
123 uint32_t cfg;
124 };
125
126 /**
127 * struct stm32_risaf_pdata - RISAF platform data
128 *
129 * @base: Base address of the RISAF instance.
130 * @clock: Clock of the RISAF.
131 * @regions: Number of memory regions, defined by the device tree configuration.
132 * @risaf_name: Name of the RISAF instance
133 * @nregions: Number of memory regions found in the device tree.
134 * @conf_lock: State whether the RISAF configuration is locked.
135 * @mem_base: Base address of the memory range covered by the RISAF instance.
136 * @mem_size: Size of the memory range covered by the RISAF instance.
137 * @enc_supported: If true, the RISAF instance supports encryption of the memory
138 * regions.
139 */
140 struct stm32_risaf_pdata {
141 struct io_pa_va base;
142 struct clk *clock;
143 struct stm32_risaf_region *regions;
144 char risaf_name[20];
145 unsigned int nregions;
146 unsigned int conf_lock;
147 paddr_t mem_base;
148 size_t mem_size;
149 bool enc_supported;
150 };
151
152 /**
153 * struct stm32_risaf_ddata - RISAF driver data
154 *
155 * @mask_regions: Number of address bits to match when determining access to a
156 * base region or subregion (WIDTH).
157 * @max_base_regions: Number of subdivision of the memory range (A.K.A memory
158 * regions) supported by the RISAF instance.
159 * @granularity: Length of the smallest possible region size.
160 */
161 struct stm32_risaf_ddata {
162 uint32_t mask_regions;
163 uint32_t max_base_regions;
164 uint32_t granularity;
165 };
166
167 struct stm32_risaf_instance {
168 struct stm32_risaf_pdata pdata;
169 struct stm32_risaf_ddata *ddata;
170
171 SLIST_ENTRY(stm32_risaf_instance) link;
172 };
173
174 struct stm32_risaf_version {
175 uint32_t major;
176 uint32_t minor;
177 uint32_t ip_id;
178 uint32_t size_id;
179 };
180
181 /**
182 * struct stm32_risaf_compat_data - Describes RISAF associated data
183 * for compatible list.
184 *
185 * @supported_encryption: identify RISAF encryption capabilities.
186 */
187 struct stm32_risaf_compat_data {
188 bool supported_encryption;
189 };
190
191 static bool is_tdcid;
192
193 static const struct stm32_risaf_compat_data stm32_risaf_compat = {
194 .supported_encryption = false,
195 };
196
197 static const struct stm32_risaf_compat_data stm32_risaf_enc_compat = {
198 .supported_encryption = true,
199 };
200
201 static SLIST_HEAD(, stm32_risaf_instance) risaf_list =
202 SLIST_HEAD_INITIALIZER(risaf_list);
203
risaf_base(struct stm32_risaf_instance * risaf)204 static vaddr_t risaf_base(struct stm32_risaf_instance *risaf)
205 {
206 return io_pa_or_va_secure(&risaf->pdata.base, 1);
207 }
208
stm32_risaf_get_region_config(uint32_t cfg)209 static uint32_t stm32_risaf_get_region_config(uint32_t cfg)
210 {
211 return SHIFT_U32((cfg & DT_RISAF_EN_MASK) >> DT_RISAF_EN_SHIFT,
212 _RISAF_REG_CFGR_BREN_SHIFT) |
213 SHIFT_U32((cfg & DT_RISAF_SEC_MASK) >> DT_RISAF_SEC_SHIFT,
214 _RISAF_REG_CFGR_SEC_SHIFT) |
215 SHIFT_U32((cfg & DT_RISAF_ENC_MASK) >> (DT_RISAF_ENC_SHIFT + 1),
216 _RISAF_REG_CFGR_ENC_SHIFT) |
217 SHIFT_U32((cfg & DT_RISAF_PRIV_MASK) >> DT_RISAF_PRIV_SHIFT,
218 _RISAF_REG_CFGR_PRIVC_SHIFT);
219 }
220
stm32_risaf_get_region_cid_config(uint32_t cfg)221 static uint32_t stm32_risaf_get_region_cid_config(uint32_t cfg)
222 {
223 return SHIFT_U32((cfg & DT_RISAF_WRITE_MASK) >> DT_RISAF_WRITE_SHIFT,
224 _RISAF_REG_CIDCFGR_WRENC_SHIFT) |
225 SHIFT_U32((cfg & DT_RISAF_READ_MASK) >> DT_RISAF_READ_SHIFT,
226 _RISAF_REG_CIDCFGR_RDENC_SHIFT);
227 }
228
stm32_risaf_clear_illegal_access_flags(void)229 void stm32_risaf_clear_illegal_access_flags(void)
230 {
231 struct stm32_risaf_instance *risaf = NULL;
232
233 SLIST_FOREACH(risaf, &risaf_list, link) {
234 vaddr_t base = io_pa_or_va_secure(&risaf->pdata.base, 1);
235
236 if (!io_read32(base + _RISAF_IASR))
237 continue;
238
239 io_write32(base + _RISAF_IACR, _RISAF_IACR_CAEF |
240 _RISAF_IACR_IAEF0 | _RISAF_IACR_IAEF1);
241 }
242 }
243
stm32_risaf_print_erroneous_data(void)244 void stm32_risaf_print_erroneous_data(void)
245 {
246 struct stm32_risaf_instance *risaf = NULL;
247
248 if (!IS_ENABLED(CFG_TEE_CORE_DEBUG))
249 return;
250
251 SLIST_FOREACH(risaf, &risaf_list, link) {
252 vaddr_t base = io_pa_or_va_secure(&risaf->pdata.base, 1);
253
254 /* Check if faulty address on this RISAF */
255 if (!io_read32(base + _RISAF_IASR))
256 continue;
257
258 IMSG("\n\nDUMPING DATA FOR %s\n\n", risaf->pdata.risaf_name);
259 IMSG("=====================================================");
260 IMSG("Status register (IAESR0): %#"PRIx32,
261 io_read32(base + _RISAF_IAESR0));
262
263 /* Reserved if dual port feature not available */
264 if (io_read32(base + _RISAF_IAESR1))
265 IMSG("Status register Dual Port (IAESR1) %#"PRIx32,
266 io_read32(base + _RISAF_IAESR1));
267
268 IMSG("-----------------------------------------------------");
269 if (virt_to_phys((void *)base) == RISAF4_BASE) {
270 IMSG("Faulty address (IADDR0): %#"PRIxPA,
271 risaf->pdata.mem_base +
272 io_read32(base + _RISAF_IADDR0));
273
274 /* Reserved if dual port feature not available */
275 if (io_read32(base + _RISAF_IADDR1))
276 IMSG("Dual port faulty address (IADDR1): %#"PRIxPA,
277 risaf->pdata.mem_base +
278 io_read32(base + _RISAF_IADDR1));
279 } else {
280 IMSG("Faulty address (IADDR0): %#"PRIx32,
281 io_read32(base + _RISAF_IADDR0));
282
283 /* Reserved if dual port feature not available */
284 if (io_read32(base + _RISAF_IADDR1))
285 IMSG("Dual port faulty address (IADDR1): %#"PRIx32,
286 io_read32(base + _RISAF_IADDR1));
287 }
288
289 IMSG("=====================================================\n");
290 };
291 }
292
293 static __maybe_unused
risaf_is_hw_encryption_enabled(struct stm32_risaf_instance * risaf)294 bool risaf_is_hw_encryption_enabled(struct stm32_risaf_instance *risaf)
295 {
296 return (io_read32(risaf_base(risaf) + _RISAF_SR) &
297 _RISAF_SR_ENCDIS) != _RISAF_SR_ENCDIS;
298 }
299
300 static TEE_Result
risaf_check_region_boundaries(struct stm32_risaf_instance * risaf,struct stm32_risaf_region * region)301 risaf_check_region_boundaries(struct stm32_risaf_instance *risaf,
302 struct stm32_risaf_region *region)
303 {
304 if (!core_is_buffer_inside(region->addr, region->len,
305 risaf->pdata.mem_base,
306 risaf->pdata.mem_size)) {
307 EMSG("Region %#"PRIxPA"..%#"PRIxPA" outside RISAF area %#"PRIxPA"...%#"PRIxPA,
308 region->addr, region->addr + region->len - 1,
309 risaf->pdata.mem_base,
310 risaf->pdata.mem_base + risaf->pdata.mem_size - 1);
311 return TEE_ERROR_BAD_PARAMETERS;
312 }
313
314 if (!risaf->ddata->granularity ||
315 (region->addr % risaf->ddata->granularity) ||
316 (region->len % risaf->ddata->granularity)) {
317 EMSG("RISAF %#"PRIxPA": start/end address granularity not respected",
318 risaf->pdata.base.pa);
319 return TEE_ERROR_BAD_PARAMETERS;
320 }
321
322 return TEE_SUCCESS;
323 }
324
325 static TEE_Result
risaf_check_overlap(struct stm32_risaf_instance * risaf __maybe_unused,struct stm32_risaf_region * region,unsigned int index)326 risaf_check_overlap(struct stm32_risaf_instance *risaf __maybe_unused,
327 struct stm32_risaf_region *region, unsigned int index)
328 {
329 unsigned int i = 0;
330
331 for (i = 0; i < index; i++) {
332 /* Skip region if there's no configuration */
333 if (!region[i].cfg)
334 continue;
335
336 if (core_is_buffer_intersect(region[index].addr,
337 region[index].len,
338 region[i].addr,
339 region[i].len)) {
340 EMSG("RISAF %#"PRIxPA": Regions %u and %u overlap",
341 risaf->pdata.base.pa, index, i);
342 return TEE_ERROR_GENERIC;
343 }
344 }
345
346 return TEE_SUCCESS;
347 }
348
risaf_configure_region(struct stm32_risaf_instance * risaf,uint32_t region_id,uint32_t cfg,uint32_t cid_cfg,paddr_t saddr,paddr_t eaddr)349 static TEE_Result risaf_configure_region(struct stm32_risaf_instance *risaf,
350 uint32_t region_id, uint32_t cfg,
351 uint32_t cid_cfg, paddr_t saddr,
352 paddr_t eaddr)
353 {
354 uint32_t mask = risaf->ddata->mask_regions;
355 vaddr_t base = risaf_base(risaf);
356
357 if (cfg & _RISAF_REG_CFGR_ENC) {
358 if (!risaf->pdata.enc_supported) {
359 EMSG("RISAF %#"PRIxPA": encryption feature error",
360 risaf->pdata.base.pa);
361 return TEE_ERROR_GENERIC;
362 }
363
364 if ((cfg & _RISAF_REG_CFGR_SEC) != _RISAF_REG_CFGR_SEC) {
365 EMSG("RISAF %#"PRIxPA": encryption on non-secure area",
366 risaf->pdata.base.pa);
367 return TEE_ERROR_GENERIC;
368 }
369 }
370
371 io_clrbits32(base + _RISAF_REG_CFGR(region_id), _RISAF_REG_CFGR_BREN);
372
373 io_clrsetbits32(base + _RISAF_REG_STARTR(region_id), mask,
374 (saddr - risaf->pdata.mem_base) & mask);
375 io_clrsetbits32(base + _RISAF_REG_ENDR(region_id), mask,
376 (eaddr - risaf->pdata.mem_base) & mask);
377 io_clrsetbits32(base + _RISAF_REG_CIDCFGR(region_id),
378 _RISAF_REG_CIDCFGR_ALL_MASK,
379 cid_cfg & _RISAF_REG_CIDCFGR_ALL_MASK);
380
381 io_clrsetbits32(base + _RISAF_REG_CFGR(region_id),
382 _RISAF_REG_CFGR_ALL_MASK,
383 cfg & _RISAF_REG_CFGR_ALL_MASK);
384
385 DMSG("RISAF %#"PRIxPA": region %02"PRIu32" - start %#"PRIxPA
386 "- end %#"PRIxPA" - cfg %#08"PRIx32" - cidcfg %#08"PRIx32,
387 risaf->pdata.base.pa, region_id,
388 risaf->pdata.mem_base +
389 io_read32(base + _RISAF_REG_STARTR(region_id)),
390 risaf->pdata.mem_base +
391 io_read32(base + _RISAF_REG_ENDR(region_id)),
392 io_read32(base + _RISAF_REG_CFGR(region_id)),
393 io_read32(base + _RISAF_REG_CIDCFGR(region_id)));
394
395 return TEE_SUCCESS;
396 }
397
risaf_print_version(struct stm32_risaf_instance * risaf)398 static void risaf_print_version(struct stm32_risaf_instance *risaf)
399 {
400 vaddr_t base = risaf_base(risaf);
401 struct stm32_risaf_version __maybe_unused version = {
402 .major = (io_read32(base + _RISAF_VERR) &
403 _RISAF_VERR_MAJREV_MASK) >> _RISAF_VERR_MAJREV_SHIFT,
404 .minor = (io_read32(base + _RISAF_VERR) &
405 _RISAF_VERR_MINREV_MASK) >> _RISAF_VERR_MINREV_SHIFT,
406 .ip_id = io_read32(base + _RISAF_IPIDR),
407 .size_id = io_read32(base + _RISAF_SIDR)
408 };
409
410 DMSG("RISAF %#"PRIxPA" version %"PRIu32".%"PRIu32", ip%#"PRIx32" size%#"PRIx32,
411 risaf->pdata.base.pa, version.major, version.minor, version.ip_id,
412 version.size_id);
413 }
414
415 static __maybe_unused
stm32_risaf_lock(struct stm32_risaf_instance * risaf)416 void stm32_risaf_lock(struct stm32_risaf_instance *risaf)
417 {
418 assert(risaf);
419
420 io_setbits32(risaf_base(risaf) + _RISAF_CR, _RISAF_CR_GLOCK);
421 }
422
423 static __maybe_unused
stm32_risaf_is_locked(struct stm32_risaf_instance * risaf,bool * state)424 void stm32_risaf_is_locked(struct stm32_risaf_instance *risaf, bool *state)
425 {
426 assert(risaf);
427
428 *state = (io_read32(risaf_base(risaf) + _RISAF_CR) &
429 _RISAF_CR_GLOCK) == _RISAF_CR_GLOCK;
430 }
431
stm32_risaf_init_ddata(struct stm32_risaf_instance * risaf)432 static TEE_Result stm32_risaf_init_ddata(struct stm32_risaf_instance *risaf)
433 {
434 vaddr_t base = risaf_base(risaf);
435 uint32_t granularity = 0;
436 uint32_t mask_lsb = 0;
437 uint32_t mask_msb = 0;
438 uint32_t hwcfgr = 0;
439
440 risaf->ddata = calloc(1, sizeof(*risaf->ddata));
441 if (!risaf->ddata)
442 return TEE_ERROR_OUT_OF_MEMORY;
443
444 /* Get address mask depending on RISAF instance HW configuration */
445 hwcfgr = io_read32(base + _RISAF_HWCFGR);
446 mask_lsb = (hwcfgr & _RISAF_HWCFGR_CFG3_MASK) >>
447 _RISAF_HWCFGR_CFG3_SHIFT;
448 mask_msb = mask_lsb + ((hwcfgr & _RISAF_HWCFGR_CFG4_MASK) >>
449 _RISAF_HWCFGR_CFG4_SHIFT) - 1U;
450 risaf->ddata->mask_regions = GENMASK_32(mask_msb, mask_lsb);
451 risaf->ddata->max_base_regions = (hwcfgr & _RISAF_HWCFGR_CFG1_MASK) >>
452 _RISAF_HWCFGR_CFG1_SHIFT;
453
454 /* Get IP region granularity */
455 granularity = io_read32(risaf_base(risaf) + _RISAF_HWCFGR);
456 granularity = BIT((granularity & _RISAF_HWCFGR_CFG3_MASK) >>
457 _RISAF_HWCFGR_CFG3_SHIFT);
458 risaf->ddata->granularity = granularity;
459
460 return TEE_SUCCESS;
461 }
462
stm32_risaf_pm_resume(struct stm32_risaf_instance * risaf)463 static TEE_Result stm32_risaf_pm_resume(struct stm32_risaf_instance *risaf)
464 {
465 struct stm32_risaf_region *regions = risaf->pdata.regions;
466 size_t i = 0;
467
468 for (i = 0; i < risaf->pdata.nregions; i++) {
469 uint32_t id = _RISAF_GET_REGION_ID(regions[i].cfg);
470 paddr_t start_addr = 0;
471 paddr_t end_addr = 0;
472 uint32_t cid_cfg = 0;
473 uint32_t cfg = 0;
474
475 if (!id)
476 continue;
477
478 cfg = stm32_risaf_get_region_config(regions[i].cfg);
479 cid_cfg = stm32_risaf_get_region_cid_config(regions[i].cfg);
480 start_addr = regions[i].addr;
481 end_addr = start_addr + regions[i].len - 1U;
482 if (risaf_configure_region(risaf, id, cfg, cid_cfg,
483 start_addr, end_addr))
484 panic();
485 }
486
487 return TEE_SUCCESS;
488 }
489
stm32_risaf_pm_suspend(struct stm32_risaf_instance * risaf)490 static TEE_Result stm32_risaf_pm_suspend(struct stm32_risaf_instance *risaf)
491 {
492 vaddr_t base = io_pa_or_va_secure(&risaf->pdata.base, 1);
493 size_t i = 0;
494
495 for (i = 0; i < risaf->pdata.nregions; i++) {
496 uint32_t id = _RISAF_GET_REGION_ID(risaf->pdata.regions[i].cfg);
497 struct stm32_risaf_region *region = risaf->pdata.regions + i;
498 paddr_t start_addr = 0;
499 paddr_t end_addr = 0;
500 uint32_t cid_cfg = 0;
501 uint32_t priv = 0;
502 uint32_t rden = 0;
503 uint32_t wren = 0;
504 uint32_t cfg = 0;
505 uint32_t enc = 0;
506 uint32_t sec = 0;
507 uint32_t en = 0;
508
509 /* Skip region not defined in DT, not configured in probe */
510 if (!id)
511 continue;
512
513 cfg = io_read32(base + _RISAF_REG_CFGR(id));
514 en = cfg & _RISAF_REG_CFGR_BREN;
515 sec = (cfg & _RISAF_REG_CFGR_SEC) >> _RISAF_REG_CFGR_SEC_SHIFT;
516 enc = (cfg & _RISAF_REG_CFGR_ENC) >> _RISAF_REG_CFGR_ENC_SHIFT;
517 priv = (cfg & _RISAF_REG_CFGR_PRIVC_MASK) >>
518 _RISAF_REG_CFGR_PRIVC_SHIFT;
519
520 cid_cfg = io_read32(base + _RISAF_REG_CIDCFGR(id));
521 rden = cid_cfg & _RISAF_REG_CIDCFGR_RDENC_MASK;
522 wren = (cid_cfg & _RISAF_REG_CIDCFGR_WRENC_MASK) >>
523 _RISAF_REG_CIDCFGR_WRENC_SHIFT;
524
525 region->cfg = id | SHIFT_U32(en, DT_RISAF_EN_SHIFT) |
526 SHIFT_U32(sec, DT_RISAF_SEC_SHIFT) |
527 SHIFT_U32(enc, DT_RISAF_ENC_SHIFT + 1) |
528 SHIFT_U32(priv, DT_RISAF_PRIV_SHIFT) |
529 SHIFT_U32(rden, DT_RISAF_READ_SHIFT) |
530 SHIFT_U32(wren, DT_RISAF_WRITE_SHIFT);
531 start_addr = io_read32(base + _RISAF_REG_STARTR(id));
532 end_addr = io_read32(base + _RISAF_REG_ENDR(id));
533 region->addr = start_addr + risaf->pdata.mem_base;
534 region->len = end_addr - start_addr + 1;
535 }
536
537 return TEE_SUCCESS;
538 }
539
540 static TEE_Result
stm32_risaf_pm(enum pm_op op,unsigned int pm_hint,const struct pm_callback_handle * pm_handle)541 stm32_risaf_pm(enum pm_op op, unsigned int pm_hint,
542 const struct pm_callback_handle *pm_handle)
543 {
544 struct stm32_risaf_instance *risaf = pm_handle->handle;
545 TEE_Result res = TEE_ERROR_GENERIC;
546
547 assert(risaf);
548
549 if (!PM_HINT_IS_STATE(pm_hint, CONTEXT))
550 return TEE_SUCCESS;
551
552 if (op == PM_OP_RESUME)
553 res = stm32_risaf_pm_resume(risaf);
554 else
555 res = stm32_risaf_pm_suspend(risaf);
556
557 return res;
558 }
559
stm32_risaf_acquire_access(struct firewall_query * fw,paddr_t paddr,size_t size,bool read,bool write)560 static TEE_Result stm32_risaf_acquire_access(struct firewall_query *fw,
561 paddr_t paddr, size_t size,
562 bool read, bool write)
563 {
564 struct stm32_risaf_instance *risaf = NULL;
565 struct stm32_risaf_region *region = NULL;
566 uint32_t cidcfgr = 0;
567 unsigned int i = 0;
568 uint32_t cfgr = 0;
569 vaddr_t base = 0;
570 uint32_t id = 0;
571
572 assert(fw->ctrl->priv && (read || write));
573
574 if (paddr == TZDRAM_BASE && size == TZDRAM_SIZE)
575 return TEE_SUCCESS;
576
577 risaf = fw->ctrl->priv;
578 base = risaf_base(risaf);
579
580 if (fw->arg_count != 1)
581 return TEE_ERROR_BAD_PARAMETERS;
582
583 /*
584 * RISAF region configuration, we assume the query is as
585 * follows:
586 * firewall->args[0]: Region configuration
587 */
588 id = _RISAF_GET_REGION_ID(fw->args[0]);
589
590 if (!id || id >= risaf->pdata.nregions)
591 return TEE_ERROR_BAD_PARAMETERS;
592
593 for (i = 0; i < risaf->pdata.nregions; i++) {
594 if (id == _RISAF_GET_REGION_ID(risaf->pdata.regions[i].cfg)) {
595 region = &risaf->pdata.regions[i];
596 if (region->addr != paddr || region->len != size)
597 return TEE_ERROR_GENERIC;
598 break;
599 }
600 }
601 if (!region)
602 return TEE_ERROR_ITEM_NOT_FOUND;
603
604 cfgr = io_read32(base + _RISAF_REG_CFGR(id));
605 cidcfgr = io_read32(base + _RISAF_REG_CIDCFGR(id));
606
607 /*
608 * Access is denied if the region is disabled and OP-TEE does not run as
609 * TDCID, or the region is not secure, or if it is not accessible in
610 * read and/or write mode, if requested, by OP-TEE CID.
611 */
612 if (!(cfgr & _RISAF_REG_CFGR_BREN) && !is_tdcid)
613 return TEE_ERROR_ACCESS_DENIED;
614
615 if ((cfgr & _RISAF_REG_CFGR_BREN) &&
616 (!(cfgr & _RISAF_REG_CFGR_SEC) ||
617 (read && !_RISAF_REG_READ_OK(cidcfgr, RIF_CID1)) ||
618 (write && !_RISAF_REG_WRITE_OK(cidcfgr, RIF_CID1)))) {
619 return TEE_ERROR_ACCESS_DENIED;
620 }
621
622 return TEE_SUCCESS;
623 }
624
stm32_risaf_reconfigure_region(struct firewall_query * fw,paddr_t paddr,size_t size)625 static TEE_Result stm32_risaf_reconfigure_region(struct firewall_query *fw,
626 paddr_t paddr, size_t size)
627 {
628 struct stm32_risaf_instance *risaf = NULL;
629 struct stm32_risaf_region *region = NULL;
630 TEE_Result res = TEE_ERROR_GENERIC;
631 uint32_t exceptions = 0;
632 uint32_t q_cfg = 0;
633 unsigned int i = 0;
634 uint32_t id = 0;
635
636 assert(fw->ctrl->priv);
637
638 risaf = fw->ctrl->priv;
639
640 if (fw->arg_count != 1)
641 return TEE_ERROR_BAD_PARAMETERS;
642
643 /*
644 * RISAF region configuration, we assume the query is as
645 * follows:
646 * firewall->args[0]: Region configuration
647 */
648 q_cfg = fw->args[0];
649 id = _RISAF_GET_REGION_ID(q_cfg);
650
651 if (!id || id >= risaf->pdata.nregions)
652 return TEE_ERROR_BAD_PARAMETERS;
653
654 for (i = 0; i < risaf->pdata.nregions; i++) {
655 if (id == _RISAF_GET_REGION_ID(risaf->pdata.regions[i].cfg)) {
656 region = &risaf->pdata.regions[i];
657 if (region->addr != paddr || region->len != size)
658 return TEE_ERROR_GENERIC;
659 break;
660 }
661 }
662 if (!region)
663 return TEE_ERROR_ITEM_NOT_FOUND;
664
665 DMSG("Reconfiguring %s region ID: %"PRIu32, risaf->pdata.risaf_name,
666 id);
667
668 exceptions = cpu_spin_lock_xsave(&risaf->pdata.conf_lock);
669 res = risaf_configure_region(risaf, id,
670 stm32_risaf_get_region_config(q_cfg),
671 stm32_risaf_get_region_cid_config(q_cfg),
672 region->addr,
673 region->addr + region->len - 1);
674
675 cpu_spin_unlock_xrestore(&risaf->pdata.conf_lock, exceptions);
676
677 return res;
678 }
679
680 static const struct firewall_controller_ops firewall_ops = {
681 .acquire_memory_access = stm32_risaf_acquire_access,
682 .set_memory_conf = stm32_risaf_reconfigure_region,
683 };
684
stm32_risaf_probe(const void * fdt,int node,const void * compat_data)685 static TEE_Result stm32_risaf_probe(const void *fdt, int node,
686 const void *compat_data)
687 {
688 const struct stm32_risaf_compat_data *compat = compat_data;
689 struct firewall_controller *controller = NULL;
690 struct stm32_risaf_instance *risaf = NULL;
691 struct stm32_risaf_region *regions = NULL;
692 TEE_Result res = TEE_ERROR_GENERIC;
693 struct dt_node_info dt_info = { };
694 const fdt32_t *conf_list = NULL;
695 const fdt64_t *cuint = NULL;
696 unsigned int nregions = 0;
697 unsigned int i = 0;
698 int len = 0;
699
700 res = stm32_rifsc_check_tdcid(&is_tdcid);
701 if (res)
702 return res;
703
704 if (!is_tdcid)
705 return TEE_SUCCESS;
706
707 risaf = calloc(1, sizeof(*risaf));
708 if (!risaf)
709 return TEE_ERROR_OUT_OF_MEMORY;
710
711 fdt_fill_device_info(fdt, &dt_info, node);
712 if (dt_info.reg == DT_INFO_INVALID_REG ||
713 dt_info.reg_size == DT_INFO_INVALID_REG_SIZE) {
714 free(risaf);
715 return TEE_ERROR_BAD_PARAMETERS;
716 }
717
718 risaf->pdata.base.pa = dt_info.reg;
719 io_pa_or_va_secure(&risaf->pdata.base, dt_info.reg_size);
720
721 risaf->pdata.enc_supported = compat->supported_encryption;
722
723 res = clk_dt_get_by_index(fdt, node, 0, &risaf->pdata.clock);
724 if (!risaf->pdata.clock)
725 goto err;
726
727 conf_list = fdt_getprop(fdt, node, "memory-region", &len);
728 if (!conf_list) {
729 DMSG("RISAF %#"PRIxPA": No configuration in DT, use default",
730 risaf->pdata.base.pa);
731 free(risaf);
732 return TEE_SUCCESS;
733 }
734
735 nregions = (unsigned int)len / sizeof(uint32_t);
736
737 /* Silently allow unexpected truncated names */
738 strncpy(risaf->pdata.risaf_name, fdt_get_name(fdt, node, NULL),
739 sizeof(risaf->pdata.risaf_name) - 1);
740
741 res = clk_enable(risaf->pdata.clock);
742 if (res)
743 goto err;
744
745 res = stm32_risaf_init_ddata(risaf);
746 if (res)
747 goto err_clk;
748
749 risaf_print_version(risaf);
750
751 cuint = fdt_getprop(fdt, node, "st,mem-map", &len);
752 if (!cuint || (size_t)len != sizeof(*cuint) * 2)
753 panic();
754
755 risaf->pdata.mem_base = (paddr_t)fdt64_to_cpu(*cuint);
756 risaf->pdata.mem_size = (size_t)fdt64_to_cpu(*(cuint + 1));
757
758 regions = calloc(nregions, sizeof(*regions));
759 if (nregions && !regions) {
760 res = TEE_ERROR_OUT_OF_MEMORY;
761 goto err_ddata;
762 }
763
764 DMSG("RISAF %#"PRIxPA" memory range: %#"PRIxPA" - %#"PRIxPA,
765 risaf->pdata.base.pa, risaf->pdata.mem_base,
766 risaf->pdata.mem_base + risaf->pdata.mem_size - 1);
767
768 for (i = 0; i < nregions; i++) {
769 const fdt32_t *prop = NULL;
770 paddr_t start_addr = 0;
771 paddr_t end_addr = 0;
772 uint32_t cid_cfg = 0;
773 uint32_t phandle = 0;
774 uint32_t cfg = 0;
775 uint32_t id = 0;
776 int pnode = 0;
777
778 phandle = fdt32_to_cpu(*(conf_list + i));
779 pnode = fdt_node_offset_by_phandle(fdt, phandle);
780 if (pnode < 0)
781 continue;
782
783 if (fdt_reg_info(fdt, pnode, ®ions[i].addr,
784 ®ions[i].len)) {
785 EMSG("Invalid config in node %s",
786 fdt_get_name(fdt, pnode, NULL));
787 panic();
788 }
789
790 if (!regions[i].len)
791 continue;
792
793 /*
794 * The secure bootloader is in charge of configuring RISAF
795 * related to OP-TEE secure memory. Therefore, skip OP-TEE
796 * region so that RISAF configuration cannot interfere with
797 * OP-TEE execution flow.
798 */
799 if (regions[i].addr == TZDRAM_BASE &&
800 regions[i].len == TZDRAM_SIZE) {
801 continue;
802 }
803
804 prop = fdt_getprop(fdt, pnode, "st,protreg", NULL);
805 if (!prop)
806 continue;
807
808 regions[i].cfg = fdt32_to_cpu(*prop);
809
810 if (risaf_check_region_boundaries(risaf, ®ions[i]) ||
811 risaf_check_overlap(risaf, regions, i))
812 panic();
813
814 id = _RISAF_GET_REGION_ID(regions[i].cfg);
815 assert(id < risaf->ddata->max_base_regions);
816
817 cfg = stm32_risaf_get_region_config(regions[i].cfg);
818
819 cid_cfg = stm32_risaf_get_region_cid_config(regions[i].cfg);
820
821 start_addr = regions[i].addr;
822 end_addr = start_addr + regions[i].len - 1U;
823
824 if (risaf_configure_region(risaf, id, cfg, cid_cfg,
825 start_addr, end_addr))
826 panic();
827 }
828
829 controller = calloc(1, sizeof(*controller));
830 if (!controller)
831 panic();
832
833 controller->base = &risaf->pdata.base;
834 controller->name = risaf->pdata.risaf_name;
835 controller->priv = risaf;
836 controller->ops = &firewall_ops;
837
838 risaf->pdata.regions = regions;
839 risaf->pdata.nregions = nregions;
840
841 SLIST_INSERT_HEAD(&risaf_list, risaf, link);
842
843 res = firewall_dt_controller_register(fdt, node, controller);
844 if (res)
845 panic();
846
847 register_pm_core_service_cb(stm32_risaf_pm, risaf, "stm32-risaf");
848
849 return TEE_SUCCESS;
850
851 err_ddata:
852 free(risaf->ddata);
853 err_clk:
854 clk_disable(risaf->pdata.clock);
855 err:
856 free(risaf);
857 return res;
858 }
859
860 static const struct dt_device_match risaf_match_table[] = {
861 {
862 .compatible = "st,stm32mp25-risaf",
863 .compat_data = &stm32_risaf_compat,
864 },
865 {
866 .compatible = "st,stm32mp25-risaf-enc",
867 .compat_data = &stm32_risaf_enc_compat,
868 },
869 { }
870 };
871
872 DEFINE_DT_DRIVER(risaf_dt_driver) = {
873 .name = "stm32-risaf",
874 .match_table = risaf_match_table,
875 .probe = stm32_risaf_probe,
876 };
877