1 /* 2 * Copyright (c) 2022 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #ifndef _DRIVER_SPI_H_ 8 #define _DRIVER_SPI_H_ 9 10 struct rockchip_spi { 11 u32 ctrlr0; 12 u32 ctrlr1; 13 u32 enr; 14 u32 ser; 15 u32 baudr; 16 u32 txftlr; 17 u32 rxftlr; 18 u32 txflr; 19 u32 rxflr; 20 u32 sr; 21 u32 ipr; 22 u32 imr; 23 u32 isr; 24 u32 risr; 25 u32 icr; 26 u32 dmacr; 27 u32 dmatdlr; 28 u32 dmardlr; /* 0x44 */ 29 u32 reserved[0xef]; 30 u32 txdr[0x100]; /* 0x400 */ 31 u32 rxdr[0x100]; /* 0x800 */ 32 }; 33 34 /* CTRLR0 */ 35 enum { 36 DFS_SHIFT = 0, /* Data Frame Size */ 37 DFS_MASK = 3, 38 DFS_4BIT = 0, 39 DFS_8BIT, 40 DFS_16BIT, 41 DFS_RESV, 42 43 CFS_SHIFT = 2, /* Control Frame Size */ 44 CFS_MASK = 0xf, 45 46 SCPH_SHIFT = 6, /* Serial Clock Phase */ 47 SCPH_MASK = 1, 48 SCPH_TOGMID = 0, /* SCLK toggles in middle of first data bit */ 49 SCPH_TOGSTA, /* SCLK toggles at start of first data bit */ 50 51 SCOL_SHIFT = 7, /* Serial Clock Polarity */ 52 SCOL_MASK = 1, 53 SCOL_LOW = 0, /* Inactive state of serial clock is low */ 54 SCOL_HIGH, /* Inactive state of serial clock is high */ 55 56 CSM_SHIFT = 8, /* Chip Select Mode */ 57 CSM_MASK = 0x3, 58 CSM_KEEP = 0, /* ss_n stays low after each frame */ 59 CSM_HALF, /* ss_n high for half sclk_out cycles */ 60 CSM_ONE, /* ss_n high for one sclk_out cycle */ 61 CSM_RESV, 62 63 SSN_DELAY_SHIFT = 10, /* SSN to Sclk_out delay */ 64 SSN_DELAY_MASK = 1, 65 SSN_DELAY_HALF = 0, /* 1/2 sclk_out cycle */ 66 SSN_DELAY_ONE = 1, /* 1 sclk_out cycle */ 67 68 SEM_SHIFT = 11, /* Serial Endian Mode */ 69 SEM_MASK = 1, 70 SEM_LITTLE = 0, /* little endian */ 71 SEM_BIG, /* big endian */ 72 73 FBM_SHIFT = 12, /* First Bit Mode */ 74 FBM_MASK = 1, 75 FBM_MSB = 0, /* first bit is MSB */ 76 FBM_LSB, /* first bit in LSB */ 77 78 HALF_WORD_TX_SHIFT = 13, /* Byte and Halfword Transform */ 79 HALF_WORD_MASK = 1, 80 HALF_WORD_ON = 0, /* apb 16bit write/read, spi 8bit write/read */ 81 HALF_WORD_OFF, /* apb 8bit write/read, spi 8bit write/read */ 82 83 RXDSD_SHIFT = 14, /* Rxd Sample Delay, in cycles */ 84 RXDSD_MASK = 3, 85 86 FRF_SHIFT = 16, /* Frame Format */ 87 FRF_MASK = 3, 88 FRF_SPI = 0, /* Motorola SPI */ 89 FRF_SSP, /* Texas Instruments SSP*/ 90 FRF_MICROWIRE, /* National Semiconductors Microwire */ 91 FRF_RESV, 92 93 TMOD_SHIFT = 18, /* Transfer Mode */ 94 TMOD_MASK = 3, 95 TMOD_TR = 0, /* xmit & recv */ 96 TMOD_TO, /* xmit only */ 97 TMOD_RO, /* recv only */ 98 TMOD_RESV, 99 100 OMOD_SHIFT = 20, /* Operation Mode */ 101 OMOD_MASK = 1, 102 OMOD_MASTER = 0, /* Master Mode */ 103 OMOD_SLAVE, /* Slave Mode */ 104 }; 105 106 /* SR */ 107 enum { 108 SR_MASK = 0x7f, 109 SR_BUSY = 1 << 0, 110 SR_TF_FULL = 1 << 1, 111 SR_TF_EMPT = 1 << 2, 112 SR_RF_EMPT = 1 << 3, 113 SR_RF_FULL = 1 << 4, 114 }; 115 116 #define ROCKCHIP_SPI_TIMEOUT_MS 1000 117 118 #define SPI_XFER_BEGIN BIT(0) /* Assert CS before transfer */ 119 #define SPI_XFER_END BIT(1) /* Deassert CS after transfer */ 120 #define SPI_XFER_ONCE (SPI_XFER_BEGIN | SPI_XFER_END) 121 122 /* SPI mode flags */ 123 #define SPI_CPHA BIT(0) /* clock phase */ 124 #define SPI_CPOL BIT(1) /* clock polarity */ 125 #define SPI_MODE_0 (0 | 0) /* (original MicroWire) */ 126 #define SPI_MODE_1 (0 | SPI_CPHA) 127 #define SPI_MODE_2 (SPI_CPOL | 0) 128 #define SPI_MODE_3 (SPI_CPOL | SPI_CPHA) 129 130 int rockchip_spi_probe(u8 bus, uintptr_t base_addr, u32 rsd, u32 clock_div, u32 mode); 131 int rockchip_spi_claim_bus(u8 bus); 132 void rockchip_spi_release_bus(u8 bus); 133 int rockchip_spi_xfer(u8 bus, u8 cs, unsigned int bitlen, const void *dout, void *din, unsigned long flags); 134 int rockchip_spi_write_then_read(u8 bus, u8 cs, 135 const u8 *opcode, size_t n_opcode, 136 const u8 *txbuf, u8 *rxbuf, size_t n_buf); 137 138 #endif 139