1 /* 2 * Copyright (c) 2025, Mediatek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef SPMI_COMMON_H 8 #define SPMI_COMMON_H 9 10 #include <stdint.h> 11 12 #include <platform_def.h> 13 #include "pmif_common.h" 14 15 /* Read/write byte limitation */ 16 #define PMIF_BYTECNT_MAX 2 17 18 #define SPMI_GROUP_ID 0xB 19 20 /* enum marco for cmd/channel */ 21 enum spmi_master { 22 SPMI_MASTER_0 = 0, 23 SPMI_MASTER_1, 24 SPMI_MASTER_P_1, 25 SPMI_MASTER_MAX 26 }; 27 28 enum spmi_slave { 29 SPMI_SLAVE_0 = 0, 30 SPMI_SLAVE_1, 31 SPMI_SLAVE_2, 32 SPMI_SLAVE_3, 33 SPMI_SLAVE_4, 34 SPMI_SLAVE_5, 35 SPMI_SLAVE_6, 36 SPMI_SLAVE_7, 37 SPMI_SLAVE_8, 38 SPMI_SLAVE_9, 39 SPMI_SLAVE_10, 40 SPMI_SLAVE_11, 41 SPMI_SLAVE_12, 42 SPMI_SLAVE_13, 43 SPMI_SLAVE_14, 44 SPMI_SLAVE_15, 45 SPMI_MAX_SLAVE_ID 46 }; 47 48 enum slv_type { 49 BUCK_CPU, 50 BUCK_GPU, 51 BUCK_MD, 52 BUCK_RF, 53 MAIN_PMIC, 54 BUCK_VPU, 55 SUB_PMIC, 56 CLOCK_PMIC, 57 SECOND_PMIC, 58 SLV_TYPE_MAX 59 }; 60 61 enum slv_type_id { 62 BUCK_RF_ID = 1, 63 BUCK_MD_ID = 3, 64 MAIN_PMIC_ID = 5, 65 BUCK_CPU_ID = 6, 66 BUCK_GPU_ID = 7, 67 BUCK_VPU_ID, 68 SUB_PMIC_ID = 10, 69 CLOCK_PMIC_ID = 11, 70 SECOND_PMIC_ID = 12, 71 SLV_TYPE_ID_MAX 72 }; 73 74 enum { 75 SPMI_OP_ST_BUSY = 1, 76 SPMI_OP_ST_ACK = 0, 77 SPMI_OP_ST_NACK = 1 78 }; 79 80 struct spmi_device { 81 int slvid; 82 int grpiden; 83 enum slv_type type; 84 enum slv_type_id type_id; 85 int mstid; 86 uint16_t hwcid_addr; 87 uint8_t hwcid_val; 88 uint16_t hwcid_mask; 89 uint16_t swcid_addr; 90 uint8_t swcid_val; 91 uint16_t wpk_key_addr; 92 uint16_t wpk_key_val; 93 uint16_t wpk_key_h_val; 94 uint16_t tma_key_addr; 95 uint16_t tma_key_val; 96 uint16_t tma_key_h_val; 97 uint16_t rcs_en_addr; 98 uint16_t rcs_slvid_addr; 99 struct pmif *pmif_arb; 100 }; 101 102 int spmi_command_shutdown(int mstid, struct spmi_device *dev, unsigned int grpiden); 103 #endif 104