1 /* 2 * Copyright (c) 2025, MediaTek Inc. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef MTK_SOC_TEMP_LVTS_H 8 #define MTK_SOC_TEMP_LVTS_H 9 10 /* Definition or macro function */ 11 #define THERM_MODULE_SW_CG_0_SET (INFRACFG_AO_BASE + 0x80) 12 #define THERM_MODULE_SW_CG_0_CLR (INFRACFG_AO_BASE + 0x84) 13 #define THERM_BIT (10) 14 15 #define THERMAL_REBOOT_TEMPERATURE (119000) 16 17 #define DEFAULT_EFUSE_GOLDEN_TEMP (50) 18 #define DEFAULT_EFUSE_GOLDEN_TEMP_HT (170) 19 #define DEFAULT_EFUSE_COUNT (35000) 20 #define DEFAULT_EFUSE_COUNT_RC (2750) 21 22 /* LVTS reset address */ 23 #define THERM_AP_RESET_SET_OFFSET 0xf50 24 #define THERM_AP_RESET_CLR_OFFSET 0xf54 25 #define THERM_AP_RESET_SET_BITNUM 23 26 #define THERM_AP_RESET_CLR_BITNUM 23 27 28 #define THERM_MCU_RESET_SET_OFFSET 0xf20 29 #define THERM_MCU_RESET_CLR_OFFSET 0xf24 30 #define THERM_MCU_RESET_SET_BITNUM 12 31 #define THERM_MCU_RESET_CLR_BITNUM 12 32 33 /* LVTS efuse address */ 34 #define NUM_EFUSE_ADDR 23 35 36 /* LVTS v1 common code */ 37 #define SET_LVTS_MANUAL_RCK_V1 (DEVICE_WRITE | RG_TSV2F_CTRL_6 << 8 | 0x00) 38 #define SELECT_SENSOR_RCK_V1(id) (DEVICE_WRITE | RG_TSV2F_CTRL_5 << 8 | id) 39 #define KICK_OFF_RCK_COUNTING_V1 (DEVICE_WRITE | RG_TSFM_CTRL_0 << 8 | 0x02) 40 #define SET_SENSOR_NO_RCK_V1 (DEVICE_WRITE | RG_TSV2F_CTRL_5 << 8 | 0x10) 41 #define SET_DEVICE_LOW_POWER_SINGLE_MODE_V1 (DEVICE_WRITE \ 42 | RG_TSFM_CTRL_3 << 8 | 0xF8) 43 44 /* LVTS MT8189 */ 45 #define SET_DEVICE_SINGLE_MODE_8189 (DEVICE_WRITE | RG_TSFM_CTRL_3 << 8 | 0x78) 46 #define SET_TS_DIS_8189 (DEVICE_WRITE | RG_TSV2F_CTRL_0 << 8 | 0xF1) 47 #define SET_LVTS_MANUAL_RCK_OPERATION_8189 (DEVICE_WRITE \ 48 | RG_TSV2F_CTRL_6 << 8 | 0x00) 49 #define SET_TS_DIV_EN_8189 (DEVICE_WRITE | RG_TSV2F_CTRL_0 << 8 | 0xF5) 50 #define SET_VCO_RST_8189 (DEVICE_WRITE | RG_TSV2F_CTRL_0 << 8 | 0xFD) 51 #define COF_A_T_SLP_GLD 219960 52 #define COF_A_COUNT_R_GLD 14437 53 #define COF_A_CONST_OFS 280000 54 #define COF_A_OFS (COF_A_T_SLP_GLD - COF_A_CONST_OFS) 55 56 #endif /* MTK_SOC_TEMP_LVTS_H */ 57