1 /*
2 * Copyright (c) 2022, Xilinx, Inc. All rights reserved.
3 * Copyright (c) 2022-2025, Advanced Micro Devices, Inc. All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /*
9 * SoC IPI agent registers access management
10 */
11
12 #include <plat_ipi.h>
13
14 /* Versal Gen 2 ipi configuration table */
15 static const struct ipi_config ipi_table[IPI_ID_MAX] = {
16 /* A78 IPI */
17 [IPI_ID_APU] = {
18 .ipi_bit_mask = IPI0_TRIG_BIT,
19 .ipi_reg_base = IPI0_REG_BASE,
20 .secure_only = 0,
21 },
22
23 /* PMC IPI */
24 [IPI_ID_PMC] = {
25 .ipi_bit_mask = PMC_IPI_TRIG_BIT,
26 .ipi_reg_base = IPI0_REG_BASE,
27 .secure_only = IPI_SECURE_MASK,
28 },
29
30 /* RPU0 IPI */
31 [IPI_ID_RPU0] = {
32 .ipi_bit_mask = IPI1_TRIG_BIT,
33 .ipi_reg_base = IPI1_REG_BASE,
34 .secure_only = 0,
35 },
36
37 /* RPU1 IPI */
38 [IPI_ID_RPU1] = {
39 .ipi_bit_mask = IPI2_TRIG_BIT,
40 .ipi_reg_base = IPI2_REG_BASE,
41 .secure_only = 0,
42 },
43
44 /* IPI3 IPI */
45 [IPI_ID_3] = {
46 .ipi_bit_mask = IPI3_TRIG_BIT,
47 .ipi_reg_base = IPI3_REG_BASE,
48 .secure_only = 0,
49 },
50
51 /* IPI4 IPI */
52 [IPI_ID_4] = {
53 .ipi_bit_mask = IPI4_TRIG_BIT,
54 .ipi_reg_base = IPI4_REG_BASE,
55 .secure_only = 0,
56 },
57
58 /* IPI5 IPI */
59 [IPI_ID_5] = {
60 .ipi_bit_mask = IPI5_TRIG_BIT,
61 .ipi_reg_base = IPI5_REG_BASE,
62 .secure_only = 0,
63 },
64
65 /* PMC_NOBUF IPI */
66 [IPI_ID_PMC_NOBUF] = {
67 .ipi_bit_mask = PMC_NOBUF_TRIG_BIT,
68 .ipi_reg_base = PMC_NOBUF_REG_BASE,
69 .secure_only = IPI_SECURE_MASK,
70 },
71
72 /* IPI6 IPI */
73 [IPI_ID_6_NOBUF_95] = {
74 .ipi_bit_mask = IPI6_NOBUF_95_TRIG_BIT,
75 .ipi_reg_base = IPI6_NOBUF_95_REG_BASE,
76 .secure_only = 0,
77 },
78
79 /* IPI1 NO BUF IPI */
80 [IPI_ID_1_NOBUF] = {
81 .ipi_bit_mask = IPI1_NOBUF_TRIG_BIT,
82 .ipi_reg_base = IPI1_NOBUF_REG_BASE,
83 .secure_only = 0,
84 },
85
86 /* IPI2 NO BUF IPI */
87 [IPI_ID_2_NOBUF] = {
88 .ipi_bit_mask = IPI2_NOBUF_TRIG_BIT,
89 .ipi_reg_base = IPI2_NOBUF_REG_BASE,
90 .secure_only = 0,
91 },
92
93 /* IPI3 NO BUF IPI */
94 [IPI_ID_3_NOBUF] = {
95 .ipi_bit_mask = IPI3_NOBUF_TRIG_BIT,
96 .ipi_reg_base = IPI3_NOBUF_REG_BASE,
97 .secure_only = 0,
98 },
99
100 /* IPI4 NO BUF IPI */
101 [IPI_ID_4_NOBUF] = {
102 .ipi_bit_mask = IPI4_NOBUF_TRIG_BIT,
103 .ipi_reg_base = IPI4_NOBUF_REG_BASE,
104 .secure_only = 0,
105 },
106
107 /* IPI5 NO BUF IPI */
108 [IPI_ID_5_NOBUF] = {
109 .ipi_bit_mask = IPI5_NOBUF_TRIG_BIT,
110 .ipi_reg_base = IPI5_NOBUF_REG_BASE,
111 .secure_only = 0,
112 },
113
114 /* IPI6 NO BUF IPI */
115 [IPI_ID_6_NOBUF_101] = {
116 .ipi_bit_mask = IPI6_NOBUF_101_TRIG_BIT,
117 .ipi_reg_base = IPI6_NOBUF_101_REG_BASE,
118 .secure_only = 0,
119 },
120 };
121
122 /**
123 * soc_ipi_config_table_init() - Initialize Versal Gen 2 IPI configuration data.
124 */
soc_ipi_config_table_init(void)125 void soc_ipi_config_table_init(void)
126 {
127 ipi_config_table_init(ipi_table, ARRAY_SIZE(ipi_table));
128 }
129