1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd 4 */ 5 #ifndef __SOC_ROCKCHIP_PERFORMANCE_H 6 #define __SOC_ROCKCHIP_PERFORMANCE_H 7 8 enum { 9 ROCKCHIP_PERFORMANCE_LOW = 0, 10 ROCKCHIP_PERFORMANCE_NORMAL, 11 ROCKCHIP_PERFORMANCE_HIGH 12 }; 13 14 #ifdef CONFIG_ROCKCHIP_PERFORMANCE 15 extern int rockchip_perf_get_level(void); 16 extern struct cpumask *rockchip_perf_get_cpul_mask(void); 17 extern struct cpumask *rockchip_perf_get_cpub_mask(void); 18 extern int rockchip_perf_select_rt_cpu(int prev_cpu, struct cpumask *lowest_mask); 19 extern bool rockchip_perf_misfit_rt(int cpu); 20 extern void rockchip_perf_uclamp_sync_util_min_rt_default(void); 21 #else rockchip_perf_get_level(void)22static inline int rockchip_perf_get_level(void) { return ROCKCHIP_PERFORMANCE_NORMAL; } rockchip_perf_get_cpul_mask(void)23static inline struct cpumask *rockchip_perf_get_cpul_mask(void) { return NULL; }; rockchip_perf_get_cpub_mask(void)24static inline struct cpumask *rockchip_perf_get_cpub_mask(void) { return NULL; }; rockchip_perf_select_rt_cpu(int prev_cpu,struct cpumask * lowest_mask)25static inline int rockchip_perf_select_rt_cpu(int prev_cpu, struct cpumask *lowest_mask) 26 { 27 return prev_cpu; 28 } rockchip_perf_misfit_rt(int cpu)29static inline bool rockchip_perf_misfit_rt(int cpu) { return false; } rockchip_perf_uclamp_sync_util_min_rt_default(void)30static inline void rockchip_perf_uclamp_sync_util_min_rt_default(void) {} 31 #endif 32 33 #endif 34