1 /* 2 * Copyright (c) 2015 South Silicon Valley Microelectronics Inc. 3 * Copyright (c) 2015 iComm Corporation 4 * 5 * This program is free software: you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation, either version 3 of the License, or 8 * (at your option) any later version. 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 12 * See the GNU General Public License for more details. 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #ifndef _SDIO_DEF_H_ 18 #define _SDIO_DEF_H_ 19 #include <linux/scatterlist.h> 20 #define BASE_SDIO 0 21 #define REG_DATA_IO_PORT_0 (BASE_SDIO + 0x00) 22 #define REG_DATA_IO_PORT_1 (BASE_SDIO + 0x01) 23 #define REG_DATA_IO_PORT_2 (BASE_SDIO + 0x02) 24 #define REG_INT_MASK (BASE_SDIO + 0x04) 25 #define REG_INT_STATUS (BASE_SDIO + 0x08) 26 #define REG_INT_TRIGGER (BASE_SDIO + 0x09) 27 #define REG_Fn1_STATUS (BASE_SDIO + 0x0c) 28 #define REG_CARD_PKT_LEN_0 (BASE_SDIO + 0x10) 29 #define REG_CARD_PKT_LEN_1 (BASE_SDIO + 0x11) 30 #define REG_CARD_FW_DL_STATUS (BASE_SDIO + 0x12) 31 #define REG_CARD_SELF_TEST (BASE_SDIO + 0x13) 32 #define REG_CARD_RCA_0 (BASE_SDIO + 0x20) 33 #define REG_CARD_RCA_1 (BASE_SDIO + 0x21) 34 #define REG_SDIO_FIFO_WR_THLD_0 (BASE_SDIO + 0x24) 35 #define REG_SDIO_FIFO_WR_THLD_1 (BASE_SDIO + 0x25) 36 #define REG_OUTPUT_TIMING_REG (BASE_SDIO + 0x55) 37 #define REG_PMU_WAKEUP (BASE_SDIO + 0x67) 38 #define REG_REG_IO_PORT_0 (BASE_SDIO + 0x70) 39 #define REG_REG_IO_PORT_1 (BASE_SDIO + 0x71) 40 #define REG_REG_IO_PORT_2 (BASE_SDIO + 0x72) 41 #define REG_SDIO_TX_ALLOC_SIZE (BASE_SDIO + 0x98) 42 #define REG_SDIO_TX_ALLOC_SHIFT (BASE_SDIO + 0x99) 43 #define REG_SDIO_TX_ALLOC_STATE (BASE_SDIO + 0x9a) 44 #define REG_SDIO_TX_INFORM_0 (BASE_SDIO + 0x9c) 45 #define REG_SDIO_TX_INFORM_1 (BASE_SDIO + 0x9d) 46 #define REG_SDIO_TX_INFORM_2 (BASE_SDIO + 0x9e) 47 #if 0 48 #define SDIO_TX_ALLOC_SUCCESS 0x01 49 #define SDIO_TX_NO_ALLOC 0x02 50 #define SDIO_TX_DULPICATE_ALLOC 0x04 51 #define SDIO_TX_TX_DONE 0x08 52 #define SDIO_TX_AHB_HANG 0x10 53 #define SDIO_TX_MB_FULL 0x80 54 #define SDIO_HCI_IN_QUEUE_EMPTY 0x04 55 #define SDIO_EDCA0_SHIFT 4 56 #define SDIO_TX_ALLOC_SIZE_SHIFT 0x07 57 #define SDIO_TX_ALLOC_ENABLE 0x10 58 #endif 59 #define SDIO_DEF_BLOCK_SIZE 0x80 60 #if (SDIO_DEF_BLOCK_SIZE % 8) 61 #error Wrong SDIO_DEF_BLOCK_SIZE value!! Should be the multiple of 8 bytes!!!!!!!!!!!!!!!!!!!!!! 62 #endif 63 #define SDIO_DEF_OUTPUT_TIMING 0 64 #define SDIO_DEF_BLOCK_MODE_THRD 128 65 #if (SDIO_DEF_BLOCK_MODE_THRD % 8) 66 #error Wrong SDIO_DEF_BLOCK_MODE_THRD value!! Should be the multiple of 8 bytes!!!!!!!!!!!!!!!!!!!!!! 67 #endif 68 #define SDIO_DEF_FORCE_BLOCK_MODE 0 69 #define MAX_SCATTER_ENTRIES_PER_REQ 8 70 struct sdio_scatter_item { 71 u8 *buf; 72 int len; 73 }; 74 struct sdio_scatter_req { 75 u32 req; 76 u32 len; 77 int scat_entries; 78 struct sdio_scatter_item scat_list[MAX_SCATTER_ENTRIES_PER_REQ]; 79 struct scatterlist sgentries[MAX_SCATTER_ENTRIES_PER_REQ]; 80 }; 81 #define SDIO_READ 0x00000001 82 #define SDIO_WRITE 0x00000002 83 #define CMD53_ARG_READ 0 84 #define CMD53_ARG_WRITE 1 85 #define CMD53_ARG_BLOCK_BASIS 1 86 #define CMD53_ARG_FIXED_ADDRESS 0 87 #define CMD53_ARG_INCR_ADDRESS 1 88 #ifdef CONFIG_FW_ALIGNMENT_CHECK 89 #define SDIO_DMA_BUFFER_LEN 2048 90 #endif 91 #ifdef CONFIG_PM 92 #define SDIO_COMMAND_BUFFER_LEN 256 93 #endif 94 #endif 95