1 /* 2 * SPROM format definitions for the Broadcom 47xx and 43xx chip family. 3 * Broadcom Proprietary and Confidential. Copyright (C) 2020, 4 * All Rights Reserved. 5 * 6 * This is UNPUBLISHED PROPRIETARY SOURCE CODE of Broadcom; 7 * the contents of this file may not be disclosed to third parties, 8 * copied or duplicated in any form, in whole or in part, without 9 * the prior written permission of Broadcom. 10 * 11 * 12 * <<Broadcom-WL-IPTag/Proprietary:>> 13 */ 14 15 #ifndef _SBSPROM_H 16 #define _SBSPROM_H 17 18 #include "typedefs.h" 19 #include "bcmdevs.h" 20 21 /* A word is this many bytes */ 22 #define SRW 2 23 24 /* offset into PCI config space for write enable bit */ 25 #define CFG_SROM_WRITABLE_OFFSET 0x88 26 #define SROM_WRITEABLE 0x10 27 28 /* enumeration space consists of N contiguous 4Kbyte core register sets */ 29 #define SBCORES_BASE 0x18000000 30 #define SBCORES_EACH 0x1000 31 32 /* offset from BAR0 for srom space */ 33 #define SROM_BASE 4096 34 35 /* number of 2-byte words in srom */ 36 #define SROM_SIZE 64 37 38 #define SROM_BYTES (SROM_SIZE * SRW) 39 40 #define MAX_FN 4 41 42 /* Word 0, Hardware control */ 43 #define SROM_HWCTL 0 44 #define HW_FUNMSK 0x000f 45 #define HW_FCLK 0x0200 46 #define HW_CBM 0x0400 47 #define HW_PIMSK 0xf000 48 #define HW_PISHIFT 12 49 #define HW_PI4402 0x2 50 #define HW_FUN4401 0x0001 51 #define HW_FCLK4402 0x0000 52 53 /* Word 1, common-power/boot-rom */ 54 #define SROM_COMMPW 1 55 /* boot rom present bit */ 56 #define BR_PRESSHIFT 8 57 /* 15:9 for n; boot rom size is 2^(14 + n) bytes */ 58 #define BR_SIZESHIFT 9 59 60 /* Word 2, SubsystemId */ 61 #define SROM_SSID 2 62 63 /* Word 3, VendorId */ 64 #define SROM_VID 3 65 66 /* Function 0 info, function info length */ 67 #define SROM_FN0 4 68 #define SROM_FNSZ 8 69 70 /* Within each function: */ 71 /* Word 0, deviceID */ 72 #define SRFN_DID 0 73 74 /* Words 1-2, ClassCode */ 75 #define SRFN_CCL 1 76 /* Word 2, D0 Power */ 77 #define SRFN_CCHD0 2 78 79 /* Word 3, PME and D1D2D3 power */ 80 #define SRFN_PMED123 3 81 82 #define PME_IL 0 83 #define PME_ENET0 1 84 #define PME_ENET1 2 85 #define PME_CODEC 3 86 87 #define PME_4402_ENET 0 88 #define PME_4402_CODEC 1 89 #define PMEREP_4402_ENET (PMERD3CV | PMERD3CA | PMERD3H | PMERD2 | PMERD1 | PMERD0 | PME) 90 91 /* Word 4, Bar1 enable, pme reports */ 92 #define SRFN_B1PMER 4 93 #define B1E 1 94 #define B1SZMSK 0xe 95 #define B1SZSH 1 96 #define PMERMSK 0x0ff0 97 #define PME 0x0010 98 #define PMERD0 0x0020 99 #define PMERD1 0x0040 100 #define PMERD2 0x0080 101 #define PMERD3H 0x0100 102 #define PMERD3CA 0x0200 103 #define PMERD3CV 0x0400 104 #define IGNCLKRR 0x0800 105 #define B0LMSK 0xf000 106 107 /* Words 4-5, Bar0 Sonics value */ 108 #define SRFN_B0H 5 109 /* Words 6-7, CIS Pointer */ 110 #define SRFN_CISL 6 111 #define SRFN_CISH 7 112 113 /* Words 36-38: iLine MAC address */ 114 #define SROM_I_MACHI 36 115 #define SROM_I_MACMID 37 116 #define SROM_I_MACLO 38 117 118 /* Words 36-38: wireless0 MAC address on 43xx */ 119 #define SROM_W0_MACHI 36 120 #define SROM_W0_MACMID 37 121 #define SROM_W0_MACLO 38 122 123 /* Words 39-41: enet0 MAC address */ 124 #define SROM_E0_MACHI 39 125 #define SROM_E0_MACMID 40 126 #define SROM_E0_MACLO 41 127 128 /* Words 42-44: enet1 MAC address */ 129 #define SROM_E1_MACHI 42 130 #define SROM_E1_MACMID 43 131 #define SROM_E1_MACLO 44 132 133 #define SROM_EPHY 45 134 135 /* Words 47-51 wl0 PA bx */ 136 #define SROM_WL0_PAB0 47 137 #define SROM_WL0_PAB1 48 138 #define SROM_WL0_PAB2 49 139 #define SROM_WL0_PAB3 50 140 #define SROM_WL0_PAB4 51 141 142 /* Word 52: wl0/wl1 MaxPower */ 143 #define SROM_WL_MAXPWR 52 144 145 /* Words 53-55 wl1 PA bx */ 146 #define SROM_WL1_PAB0 53 147 #define SROM_WL1_PAB1 54 148 #define SROM_WL1_PAB2 55 149 150 /* Woprd 56: itt */ 151 #define SROM_ITT 56 152 153 /* Words 59-62: OEM Space */ 154 #define SROM_WL_OEM 59 155 #define SROM_OEM_SIZE 4 156 157 /* Contents for the srom */ 158 159 #define BU4710_SSID 0x0400 160 #define VSIM4710_SSID 0x0401 161 #define QT4710_SSID 0x0402 162 163 #define BU4610_SSID 0x0403 164 #define VSIM4610_SSID 0x0404 165 166 #define BU4402_SSID 0x4402 167 168 #define CLASS_OTHER 0x8000 169 #define CLASS_ETHER 0x0000 170 #define CLASS_NET 0x0002 171 #define CLASS_COMM 0x0007 172 #define CLASS_MODEM 0x0300 173 #define CLASS_MIPS 0x3000 174 #define CLASS_PROC 0x000b 175 #define CLASS_FLASH 0x0100 176 #define CLASS_MEM 0x0005 177 #define CLASS_SERIALBUS 0x000c 178 #define CLASS_OHCI 0x0310 179 180 /* Broadcom IEEE MAC addresses are 00:90:4c:xx:xx:xx */ 181 #define MACHI 0x90 182 183 #define MACMID_BU4710I 0x4c17 184 #define MACMID_BU4710E0 0x4c18 185 #define MACMID_BU4710E1 0x4c19 186 187 #define MACMID_94710R1I 0x4c1a 188 #define MACMID_94710R1E0 0x4c1b 189 #define MACMID_94710R1E1 0x4c1c 190 191 #define MACMID_94710R4I 0x4c1d 192 #define MACMID_94710R4E0 0x4c1e 193 #define MACMID_94710R4E1 0x4c1f 194 195 #define MACMID_94710DEVI 0x4c20 196 #define MACMID_94710DEVE0 0x4c21 197 #define MACMID_94710DEVE1 0x4c22 198 199 #define MACMID_BU4402 0x4c23 200 201 #define MACMID_BU4610I 0x4c24 202 #define MACMID_BU4610E0 0x4c25 203 #define MACMID_BU4610E1 0x4c26 204 205 #define MACMID_BU4401 0x4c37 206 207 /* Enet phy settings one or two singles or a dual */ 208 /* Bits 4-0 : MII address for enet0 (0x1f for not there */ 209 /* Bits 9-5 : MII address for enet1 (0x1f for not there */ 210 /* Bit 14 : Mdio for enet0 */ 211 /* Bit 15 : Mdio for enet1 */ 212 213 /* bu4710 with only one phy on enet1 with address 7: */ 214 #define SROM_EPHY_ONE 0x80ff 215 216 /* bu4710 with two individual phys, at 6 and 7, */ 217 /* each mdio connected to its own mac: */ 218 #define SROM_EPHY_TWO 0x80e6 219 220 /* bu4710 with a dual phy addresses 0 & 1, mdio-connected to enet0 */ 221 /* bringup board has phyaddr0 and phyaddr1 swapped */ 222 #define SROM_EPHY_DUAL 0x0001 223 224 /* r1 board with a dual phy at 0, 1 (NOT swapped and mdc0 */ 225 #define SROM_EPHY_R1 0x0010 226 227 /* r4 board with a single phy on enet0 at address 5 and a switch */ 228 /* chip on enet1 (speciall case: 0x1e */ 229 #define SROM_EPHY_R4 0x83e5 230 231 /* 4402 uses an internal phy at phyaddr 1; want mdcport == coreunit == 0 */ 232 #define SROM_EPHY_INTERNAL 0x0001 233 234 #define SROM_VERS 0x0001 235 236 #endif /* _SBSPROM_H */ 237