1/* 2 * (C) Copyright 2020 Rockchip Electronics Co., Ltd 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7/ { 8 aliases { 9 mmc0 = &emmc; 10 mmc1 = &sdmmc; 11 }; 12 13 chosen { 14 stdout-path = &uart2; 15 u-boot,spl-boot-order = &sdmmc, &spi_nand, &spi_nor, &nandc, &emmc; 16 }; 17 18 secure-otp@ff5d0000 { 19 compatible = "rockchip,rv1126-secure-otp"; 20 reg = <0xff5d0000 0x4000>; 21 secure_conf = <0xfe0a0008>; 22 u-boot,dm-spl; 23 status = "okay"; 24 }; 25}; 26 27&psci { 28 u-boot,dm-pre-reloc; 29 status = "okay"; 30}; 31 32&uart2 { 33 clock-frequency = <24000000>; 34 u-boot,dm-spl; 35 /delete-property/ pinctrl-names; 36 /delete-property/ pinctrl-0; 37}; 38 39&sdmmc { 40 u-boot,dm-spl; 41 status = "okay"; 42}; 43 44&sdmmc0 { 45 u-boot,dm-spl; 46}; 47 48&sdmmc0_bus4 { 49 u-boot,dm-spl; 50}; 51 52&sdmmc0_clk { 53 u-boot,dm-spl; 54}; 55 56&sdmmc0_cmd { 57 u-boot,dm-spl; 58}; 59 60&sdmmc0_det { 61 u-boot,dm-spl; 62}; 63 64&emmc { 65 mmc-ecsd = <0x0020f000>; 66 u-boot,dm-spl; 67 /delete-property/ pinctrl-names; 68 /delete-property/ pinctrl-0; 69}; 70 71&pmu { 72 u-boot,dm-spl; 73}; 74 75&pmugrf { 76 u-boot,dm-spl; 77}; 78 79&pmucru { 80 u-boot,dm-spl; 81}; 82 83&cru { 84 u-boot,dm-spl; 85 /delete-property/ assigned-clocks; 86 /delete-property/ assigned-clock-rates; 87 /delete-property/ assigned-clock-parents; 88}; 89 90&crypto { 91 u-boot,dm-spl; 92 status = "okay"; 93}; 94 95&grf { 96 u-boot,dm-spl; 97}; 98 99&saradc { 100 u-boot,dm-spl; 101 status = "okay"; 102}; 103 104&sfc { 105 u-boot,dm-spl; 106 /delete-property/ pinctrl-names; 107 /delete-property/ pinctrl-0; 108 /delete-property/ assigned-clocks; 109 /delete-property/ assigned-clock-rates; 110 status = "okay"; 111 112 #address-cells = <1>; 113 #size-cells = <0>; 114 spi_nand: flash@0 { 115 u-boot,dm-spl; 116 compatible = "spi-nand"; 117 reg = <0>; 118 spi-tx-bus-width = <1>; 119 spi-rx-bus-width = <4>; 120 spi-max-frequency = <96000000>; 121 }; 122 123 spi_nor: flash@1 { 124 u-boot,dm-spl; 125 compatible = "jedec,spi-nor"; 126 label = "sfc_nor"; 127 reg = <0>; 128 spi-tx-bus-width = <1>; 129 spi-rx-bus-width = <4>; 130 spi-max-frequency = <100000000>; 131 }; 132}; 133 134&nandc { 135 u-boot,dm-spl; 136 /delete-property/ pinctrl-names; 137 /delete-property/ pinctrl-0; 138 status = "okay"; 139 #address-cells = <1>; 140 #size-cells = <0>; 141 142 nand@0 { 143 u-boot,dm-spl; 144 reg = <0>; 145 nand-ecc-mode = "hw"; 146 nand-ecc-strength = <16>; 147 nand-ecc-step-size = <1024>; 148 }; 149}; 150 151&hw_decompress { 152 u-boot,dm-spl; 153 status = "okay"; 154}; 155 156&i2c0 { 157 u-boot,dm-spl; 158 status = "okay"; 159 rk817_fg@20 { 160 u-boot,dm-spl; 161 compatible = "rk817,battery"; 162 reg = <0x20>; 163 bat_res_up = <140>; 164 bat_res_down = <20>; 165 }; 166}; 167 168&u2phy0 { 169 u-boot,dm-pre-reloc; 170 status = "okay"; 171}; 172 173&u2phy_otg { 174 u-boot,dm-pre-reloc; 175 status = "okay"; 176}; 177 178&usbdrd { 179 u-boot,dm-pre-reloc; 180 status = "okay"; 181}; 182 183&usbdrd_dwc3 { 184 u-boot,dm-pre-reloc; 185 status = "okay"; 186}; 187 188&pinctrl { 189 u-boot,dm-spl; 190 status = "okay"; 191}; 192 193&gpio0 { 194 u-boot,dm-spl; 195 status = "okay"; 196}; 197 198&gpio1 { 199 u-boot,dm-spl; 200 status = "okay"; 201}; 202 203&pcfg_pull_up_drv_level_2 { 204 u-boot,dm-spl; 205}; 206 207&pcfg_pull_none { 208 u-boot,dm-spl; 209}; 210 211&gpio3 { 212 u-boot,dm-pre-reloc; 213 status = "okay"; 214}; 215 216&gmac { 217 u-boot,dm-pre-reloc; 218 219 phy-mode = "rgmii"; 220 clock_in_out = "input"; 221 222 snps,reset-gpio = <&gpio3 RK_PA0 GPIO_ACTIVE_LOW>; 223 snps,reset-active-low; 224 /* Reset time is 20ms, 100ms for rtl8211f */ 225 snps,reset-delays-us = <0 20000 100000>; 226 227 assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_ETHERNET_OUT>; 228 assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>; 229 assigned-clock-rates = <125000000>, <0>, <25000000>; 230 231 pinctrl-names = "default"; 232 pinctrl-0 = <&rgmiim1_pins &clk_out_ethernetm1_pins>; 233 234 tx_delay = <0x2a>; 235 rx_delay = <0x1a>; 236 237 phy-handle = <&phy>; 238 status = "okay"; 239}; 240 241&mdio { 242 u-boot,dm-pre-reloc; 243 status = "okay"; 244 245 phy: phy@0 { 246 compatible = "ethernet-phy-ieee802.3-c22"; 247 u-boot,dm-pre-reloc; 248 reg = <0x0>; 249 clocks = <&cru CLK_GMAC_ETHERNET_OUT>; 250 }; 251}; 252 253&stmmac_axi_setup { 254 u-boot,dm-pre-reloc; 255 status = "okay"; 256 queue0 { 257 u-boot,dm-pre-reloc; 258 }; 259}; 260 261&mtl_rx_setup { 262 u-boot,dm-pre-reloc; 263 status = "okay"; 264 queue0 { 265 u-boot,dm-pre-reloc; 266 }; 267}; 268 269&mtl_tx_setup { 270 u-boot,dm-pre-reloc; 271 status = "okay"; 272}; 273 274&gmac_clkin_m0 { 275 u-boot,dm-pre-reloc; 276 status = "okay"; 277}; 278 279&gmac_clkini_m1 { 280 u-boot,dm-pre-reloc; 281 status = "okay"; 282}; 283 284&rgmiim1_pins { 285 u-boot,dm-pre-reloc; 286 status = "okay"; 287}; 288 289&rng { 290 u-boot,dm-spl; 291 status = "okay"; 292}; 293 294&clk_out_ethernetm1_pins{ 295 u-boot,dm-pre-reloc; 296 status = "okay"; 297}; 298 299&pcfg_pull_none { 300 u-boot,dm-pre-reloc; 301 status = "okay"; 302}; 303 304&pcfg_pull_none_drv_level_12 { 305 u-boot,dm-pre-reloc; 306 status = "okay"; 307}; 308 309&wdt { 310 u-boot,dm-pre-reloc; 311 status = "okay"; 312}; 313