xref: /OK3568_Linux_fs/u-boot/arch/arm/dts/rv1106-u-boot.dtsi (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1/*
2 * (C) Copyright 2022 Rockchip Electronics Co., Ltd
3 *
4 * SPDX-License-Identifier:     GPL-2.0+
5 */
6
7/ {
8	aliases {
9		mmc1 = &sdmmc;
10		mmc0 = &emmc;
11	};
12
13	chosen {
14		stdout-path = &uart2;
15		u-boot,spl-boot-order = &sdmmc, &spi_nor, &spi_nand, &emmc;
16	};
17
18	secure-otp@ff3fd8000 {
19		compatible = "rockchip,rv1106-secure-otp";
20		reg = <0xff3d8000 0x4000>;
21		secure_conf = <0xff07a018>;
22		cru_rst_addr = <0xff3bca08>;
23		mask_addr = <0xff3dc000>;
24		u-boot,dm-spl;
25		status = "okay";
26	};
27};
28
29&emmc {
30	mmc-ecsd = <0x3F000>;
31	bus-width = <8>;
32	mmc-hs200-1_8v;
33	u-boot,dm-spl;
34	status = "okay";
35};
36
37&cru {
38	u-boot,dm-spl;
39	status = "okay";
40};
41
42&gmac {
43	u-boot,dm-spl;
44	status = "okay";
45};
46
47&grf {
48	u-boot,dm-spl;
49	status = "okay";
50};
51
52&grf_cru {
53	u-boot,dm-spl;
54	status = "okay";
55};
56
57&mdio {
58	u-boot,dm-spl;
59	status = "okay";
60};
61
62&rmii_phy {
63	u-boot,dm-spl;
64	status = "okay";
65};
66
67&sdmmc {
68	u-boot,dm-spl;
69	status = "okay";
70};
71
72&sdmmc0 {
73	u-boot,dm-spl;
74};
75
76&sdmmc0_bus4 {
77	u-boot,dm-spl;
78};
79
80&sdmmc0_clk {
81	u-boot,dm-spl;
82};
83
84&sdmmc0_cmd {
85	u-boot,dm-spl;
86};
87
88&sdmmc0_det {
89	u-boot,dm-spl;
90};
91
92&pinctrl {
93	u-boot,dm-spl;
94	status = "okay";
95};
96
97&ioc {
98	u-boot,dm-spl;
99	status = "okay";
100};
101
102&pmuioc {
103	u-boot,dm-spl;
104	status = "okay";
105};
106
107&pcfg_pull_up_drv_level_2 {
108	u-boot,dm-spl;
109};
110
111&pcfg_pull_up {
112	u-boot,dm-spl;
113};
114
115&gpio0 {
116	u-boot,dm-pre-reloc;
117	status = "okay";
118};
119
120&gpio1 {
121	u-boot,dm-pre-reloc;
122	status = "okay";
123};
124
125&gpio2 {
126	u-boot,dm-pre-reloc;
127	status = "okay";
128};
129
130&gpio3 {
131	u-boot,dm-spl;
132	status = "okay";
133};
134
135&gpio4 {
136	u-boot,dm-pre-reloc;
137	status = "okay";
138};
139
140&crypto {
141	u-boot,dm-spl;
142	clocks = <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>;
143	clock-frequency = <300000000>, <300000000>;
144	status = "okay";
145};
146
147&rng {
148	u-boot,dm-spl;
149	status = "okay";
150};
151
152&saradc {
153	u-boot,dm-pre-reloc;
154	status = "okay";
155};
156
157&sfc {
158	u-boot,dm-spl;
159	status = "okay";
160
161	#address-cells = <1>;
162	#size-cells = <0>;
163	spi_nand: flash@0 {
164		u-boot,dm-spl;
165		compatible = "spi-nand";
166		reg = <0>;
167		spi-tx-bus-width = <1>;
168		spi-rx-bus-width = <4>;
169		spi-max-frequency = <80000000>;
170	};
171
172	spi_nor: flash@1 {
173		u-boot,dm-spl;
174		compatible = "jedec,spi-nor";
175		label = "sfc_nor";
176		reg = <0>;
177		spi-tx-bus-width = <1>;
178		spi-rx-bus-width = <4>;
179		spi-max-frequency = <100000000>;
180	};
181};
182
183&u2phy {
184	u-boot,dm-pre-reloc;
185	status = "okay";
186};
187
188&u2phy_otg {
189	u-boot,dm-pre-reloc;
190	status = "okay";
191};
192
193&usbdrd {
194	u-boot,dm-pre-reloc;
195	status = "okay";
196};
197
198&usbdrd_dwc3 {
199	u-boot,dm-pre-reloc;
200	status = "okay";
201};
202