1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2022 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/display/drm_mipi_dsi.h> 7#include <dt-bindings/input/input.h> 8 9/ { 10 vcc1v2_dvdd: vcc1v8_dovdd: vcc2v8_avdd: vcc-camera { 11 compatible = "regulator-fixed"; 12 regulator-boot-on; 13 regulator-always-on; 14 regulator-name = "vcc_camera"; 15 pinctrl-names = "default"; 16 pinctrl-0 = <&cam_pwren>; 17 enable-active-high; 18 gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_HIGH>; 19 }; 20 21 cam_ircut0: cam_ircut { 22 status = "okay"; 23 compatible = "rockchip,ircut"; 24 ircut-open-gpios = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>; 25 ircut-close-gpios = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>; 26 rockchip,camera-module-index = <0>; 27 rockchip,camera-module-facing = "back"; 28 }; 29 30 cam_ir_vcc: cam_ir_vcc-regulator { 31 compatible = "regulator-fixed"; 32 gpio = <&gpio1 RK_PA3 GPIO_ACTIVE_HIGH>; 33 pinctrl-names = "default"; 34 pinctrl-0 = <&cam_ir_pwr>; 35 regulator-name = "cam_ir_vcc"; 36 enable-active-high; 37 }; 38}; 39 40&csi2_dphy_hw { 41 status = "okay"; 42}; 43 44&csi2_dphy1 { 45 status = "okay"; 46 ports { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 port@0 { 51 reg = <0>; 52 #address-cells = <1>; 53 #size-cells = <0>; 54 55 dphy1_in: endpoint@1 { 56 reg = <1>; 57 remote-endpoint = <&gc2093_out>; 58 data-lanes = <1 2>; 59 }; 60 }; 61 62 port@1 { 63 reg = <1>; 64 #address-cells = <1>; 65 #size-cells = <0>; 66 dphy1_out: endpoint@1 { 67 reg = <1>; 68 remote-endpoint = <&mipi0_csi2_input>; 69 }; 70 }; 71 }; 72}; 73 74&csi2_dphy2 { 75 status = "okay"; 76 ports { 77 #address-cells = <1>; 78 #size-cells = <0>; 79 80 port@0 { 81 reg = <0>; 82 #address-cells = <1>; 83 #size-cells = <0>; 84 85 dphy2_in: endpoint@1 { 86 reg = <1>; 87 remote-endpoint = <&sc035gs_out>; 88 data-lanes = <1 2>; 89 }; 90 }; 91 92 port@1 { 93 reg = <1>; 94 #address-cells = <1>; 95 #size-cells = <0>; 96 97 dphy2_out: endpoint@1 { 98 reg = <1>; 99 remote-endpoint = <&mipi1_csi2_input>; 100 }; 101 }; 102 }; 103}; 104 105&i2c3 { 106 status = "okay"; 107 clock-frequency = <400000>; 108 pinctrl-names = "default"; 109 pinctrl-0 = <&i2c3m2_xfer>; 110 111 sc035gs: sc035gs@30 { 112 compatible = "smartsens,sc035gs"; 113 status = "okay"; 114 reg = <0x30>; 115 clocks = <&cru MCLK_REF_MIPI1>; 116 clock-names = "xvclk"; 117 118 reset-gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>; 119 pinctrl-names = "default"; 120 pinctrl-0 = <&mipi_refclk_out1>; 121 122 avdd-supply = <&cam_ir_vcc>; 123 124 rockchip,camera-module-index = <1>; 125 rockchip,camera-module-facing = "back"; 126 rockchip,camera-module-name = "default"; 127 rockchip,camera-module-lens-name = "default"; 128 129 port { 130 sc035gs_out: endpoint { 131 remote-endpoint = <&dphy2_in>; 132 data-lanes = <1 2>; 133 }; 134 }; 135 }; 136 137 gt24c512: gt24c512@50 { 138 compatible = "atmel,24c512"; 139 reg = <0x50>; 140 vcc-supply = <&cam_ir_vcc>; 141 }; 142 143 vcsel_rk803: vcsel_rk803@63 { 144 compatible = "rockchip,rk803"; 145 status = "okay"; 146 reg = <0x63>; 147 148 dvdd-supply = <&cam_ir_vcc>; 149 150 gpio-encc1-gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_HIGH>; //Flood 151 gpio-encc2-gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>; //PRO 152 }; 153 154}; 155 156&i2c4 { 157 rockchip,amp-shared; 158 159 status = "okay"; 160 clock-frequency = <400000>; 161 pinctrl-names = "default"; 162 pinctrl-0 = <&i2c4m2_xfer>; 163 164 gc2093: gc2093@37 { 165 compatible = "galaxycore,gc2093"; 166 status = "okay"; 167 reg = <0x37>; 168 clocks = <&cru MCLK_REF_MIPI0>; 169 clock-names = "xvclk"; 170 reset-gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_LOW>; 171 pwdn-gpios = <&gpio3 RK_PD3 GPIO_ACTIVE_HIGH>; 172 pinctrl-names = "default"; 173 pinctrl-0 = <&mipi_refclk_out0>; 174 175 avdd-supply = <&vcc2v8_avdd>; 176 dovdd-supply = <&vcc1v8_dovdd>; 177 dvdd-supply = <&vcc1v2_dvdd>; 178 179 rockchip,camera-module-index = <0>; 180 rockchip,camera-module-facing = "back"; 181 rockchip,camera-module-name = "SIDA209300461"; 182 rockchip,camera-module-lens-name = "60IRC_F20"; 183 184 lens-focus = <&cam_ircut0>; 185 186 port { 187 gc2093_out: endpoint { 188 remote-endpoint = <&dphy1_in>; 189 data-lanes = <1 2>; 190 }; 191 }; 192 }; 193}; 194 195&rkcif { 196 status = "okay"; 197}; 198 199&mipi0_csi2 { 200 status = "okay"; 201 202 ports { 203 #address-cells = <1>; 204 #size-cells = <0>; 205 206 port@0 { 207 reg = <0>; 208 #address-cells = <1>; 209 #size-cells = <0>; 210 211 mipi0_csi2_input: endpoint@1 { 212 reg = <1>; 213 remote-endpoint = <&dphy1_out>; 214 data-lanes = <1 2>; 215 }; 216 }; 217 218 port@1 { 219 reg = <1>; 220 #address-cells = <1>; 221 #size-cells = <0>; 222 223 mipi0_csi2_output: endpoint@0 { 224 reg = <0>; 225 remote-endpoint = <&cif_mipi0_in>; 226 data-lanes = <1 2>; 227 }; 228 }; 229 }; 230}; 231 232&rkcif_mipi_lvds { 233 status = "okay"; 234 235 memory-region-thunderboot = <&rkisp_thunderboot>; 236 port { 237 /* MIPI CSI-2 endpoint */ 238 cif_mipi0_in: endpoint { 239 remote-endpoint = <&mipi0_csi2_output>; 240 data-lanes = <1 2>; 241 }; 242 }; 243}; 244 245&rkcif_mipi_lvds_sditf { 246 status = "okay"; 247 248 port { 249 /* MIPI CSI-2 endpoint */ 250 mipi_lvds0_sditf: endpoint { 251 remote-endpoint = <&isp0_in>; 252 data-lanes = <1 2>; 253 }; 254 }; 255}; 256 257&mipi1_csi2 { 258 status = "okay"; 259 260 ports { 261 #address-cells = <1>; 262 #size-cells = <0>; 263 264 port@0 { 265 reg = <0>; 266 #address-cells = <1>; 267 #size-cells = <0>; 268 269 mipi1_csi2_input: endpoint@1 { 270 reg = <1>; 271 remote-endpoint = <&dphy2_out>; 272 data-lanes = <1 2>; 273 }; 274 }; 275 276 port@1 { 277 reg = <1>; 278 #address-cells = <1>; 279 #size-cells = <0>; 280 281 mipi1_csi2_output: endpoint@0 { 282 reg = <0>; 283 remote-endpoint = <&cif_mipi1_in>; 284 data-lanes = <1 2>; 285 }; 286 }; 287 }; 288}; 289 290&rkcif_mipi_lvds1 { 291 status = "okay"; 292 293 port { 294 /* MIPI CSI-2 endpoint */ 295 cif_mipi1_in: endpoint { 296 remote-endpoint = <&mipi1_csi2_output>; 297 data-lanes = <1 2>; 298 }; 299 }; 300}; 301 302&rkcif_mipi_lvds1_sditf { 303 status = "okay"; 304 port { 305 /* MIPI CSI-2 endpoint */ 306 mipi_lvds1_sditf: endpoint { 307 remote-endpoint = <&isp1_in>; 308 data-lanes = <1 2>; 309 }; 310 }; 311}; 312 313&rkisp { 314 status = "okay"; 315 316 pinctrl-names = "default"; 317 pinctrl-0 = <&mipi_pins>; 318 319 max-input = <1920 1280 30>; 320}; 321 322&mailbox { 323 status = "okay"; 324}; 325 326&thunder_boot_service { 327 status = "okay"; 328}; 329 330&rkisp_thunderboot { 331 /* vicap, capture raw10, ceil(w*10/8/256)*256*h *4(buf num) */ 332 reg = <0x00860000 0xa8c000>; 333}; 334 335&rkisp_vir0 { 336 status = "okay"; 337 338 ports { 339 port@0 { 340 isp0_in: endpoint { 341 remote-endpoint = <&mipi_lvds0_sditf>; 342 }; 343 }; 344 }; 345}; 346 347&rkisp_vir1 { 348 status = "okay"; 349 350 ports { 351 port@0 { 352 isp1_in: endpoint { 353 remote-endpoint = <&mipi_lvds1_sditf>; 354 }; 355 }; 356 }; 357}; 358 359&rkisp_vir2 { 360 status = "okay"; 361}; 362 363&pinctrl { 364 cam { 365 /* rgb camera power en */ 366 cam_pwren: cam_pwren-pwr { 367 rockchip,pins = <1 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>; 368 }; 369 370 cam_ir_pwr: cam-ir-pwr { 371 rockchip,pins = 372 /* ir camera power en */ 373 <1 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>; 374 }; 375 }; 376}; 377