1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2024 Rockchip Electronics Co., Ltd. 4 */ 5 6#include <dt-bindings/clock/rockchip,rv1103b-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/soc/rockchip,boot-mode.h> 12#include <dt-bindings/soc/rockchip-system-status.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 #address-cells = <1>; 17 #size-cells = <1>; 18 19 compatible = "rockchip,rv1103b"; 20 21 interrupt-parent = <&gic>; 22 23 aliases { 24 csi2dphy0 = &csi2_dphy0; 25 csi2dphy1 = &csi2_dphy1; 26 csi2dphy2 = &csi2_dphy2; 27 ethernet0 = &gmac; 28 gpio0 = &gpio0; 29 gpio1 = &gpio1; 30 gpio2 = &gpio2; 31 i2c0 = &i2c0; 32 i2c1 = &i2c1; 33 i2c2 = &i2c2; 34 i2c3 = &i2c3; 35 i2c4 = &i2c4; 36 mmc0 = &emmc; 37 mmc1 = &sdmmc0; 38 mmc2 = &sdmmc1; 39 rkcif_mipi_lvds0 = &rkcif_mipi_lvds; 40 rkcif_mipi_lvds1 = &rkcif_mipi_lvds1; 41 serial0 = &uart0; 42 serial1 = &uart1; 43 serial2 = &uart2; 44 spi0 = &spi0; 45 spi1 = &sfc; 46 }; 47 48 arm-pmu { 49 compatible = "arm,cortex-a7-pmu"; 50 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 51 interrupt-affinity = <&cpu0>; 52 }; 53 54 clocks { 55 compatible = "simple-bus"; 56 57 xin24m: xin24m { 58 compatible = "fixed-clock"; 59 #clock-cells = <0>; 60 clock-frequency = <24000000>; 61 clock-output-names = "xin24m"; 62 }; 63 64 xin32k: xin32k { 65 compatible = "fixed-clock"; 66 #clock-cells = <0>; 67 clock-frequency = <32768>; 68 clock-output-names = "xin32k"; 69 }; 70 }; 71 72 cpuinfo { 73 compatible = "rockchip,cpuinfo"; 74 nvmem-cells = <&otp_id>, <&otp_cpu_version>, <&cpu_code>; 75 nvmem-cell-names = "id", "cpu-version", "cpu-code"; 76 }; 77 78 cpus { 79 #address-cells = <1>; 80 #size-cells = <0>; 81 82 cpu0: cpu@0 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a7"; 85 reg = <0x0>; 86 clocks = <&cru ARMCLK>; 87 operating-points-v2 = <&cpu0_opp_table>; 88 }; 89 }; 90 91 cpu0_opp_table: cpu0-opp-table { 92 compatible = "operating-points-v2"; 93 opp-shared; 94 95 nvmem-cells = <&cpu_leakage>; 96 nvmem-cell-names = "leakage"; 97 98 opp-408000000 { 99 opp-hz = /bits/ 64 <408000000>; 100 opp-microvolt = <900000 900000 1000000>; 101 clock-latency-ns = <40000>; 102 }; 103 opp-600000000 { 104 opp-hz = /bits/ 64 <600000000>; 105 opp-microvolt = <900000 900000 1000000>; 106 clock-latency-ns = <40000>; 107 }; 108 opp-1200000000 { 109 opp-hz = /bits/ 64 <1200000000>; 110 opp-microvolt = <950000 950000 1000000>; 111 clock-latency-ns = <40000>; 112 }; 113 }; 114 115 /* dphy0 full mode */ 116 csi2_dphy0: csi2-dphy0 { 117 compatible = "rockchip,rv1106-csi2-dphy"; 118 rockchip,hw = <&csi2_dphy_hw>; 119 status = "disabled"; 120 }; 121 122 /* dphy1 split mode 01 */ 123 csi2_dphy1: csi2-dphy1 { 124 compatible = "rockchip,rv1106-csi2-dphy"; 125 rockchip,hw = <&csi2_dphy_hw>; 126 status = "disabled"; 127 }; 128 129 /* dphy2 split mode 23 */ 130 csi2_dphy2: csi2-dphy2 { 131 compatible = "rockchip,rv1106-csi2-dphy"; 132 rockchip,hw = <&csi2_dphy_hw>; 133 status = "disabled"; 134 }; 135 136 fiq_debugger: fiq-debugger { 137 compatible = "rockchip,fiq-debugger"; 138 rockchip,serial-id = <0>; 139 rockchip,wake-irq = <0>; 140 rockchip,irq-mode-enable = <0>; 141 rockchip,baudrate = <115200>; /* Only 115200 and 1500000 */ 142 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 143 status = "disabled"; 144 }; 145 146 mipi0_csi2: mipi0-csi2 { 147 compatible = "rockchip,rv1103b-mipi-csi2"; 148 rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>; 149 status = "disabled"; 150 }; 151 152 mipi1_csi2: mipi1-csi2 { 153 compatible = "rockchip,rv1103b-mipi-csi2"; 154 rockchip,hw = <&mipi0_csi2_hw>, <&mipi1_csi2_hw>; 155 status = "disabled"; 156 }; 157 158 mpp_srv: mpp-srv { 159 compatible = "rockchip,mpp-service"; 160 rockchip,taskqueue-count = <2>; 161 status = "disabled"; 162 }; 163 164 mpp_vcodec: mpp-vcodec { 165 compatible = "rockchip,vcodec"; 166 status = "disabled"; 167 }; 168 169 rkcif_mipi_lvds: rkcif-mipi-lvds { 170 compatible = "rockchip,rkcif-mipi-lvds"; 171 rockchip,hw = <&rkcif>; 172 status = "disabled"; 173 }; 174 175 rkcif_mipi_lvds_sditf: rkcif-mipi-lvds-sditf { 176 compatible = "rockchip,rkcif-sditf"; 177 rockchip,cif = <&rkcif_mipi_lvds>; 178 status = "disabled"; 179 }; 180 181 rkcif_mipi_lvds1: rkcif-mipi-lvds1 { 182 compatible = "rockchip,rkcif-mipi-lvds"; 183 rockchip,hw = <&rkcif>; 184 status = "disabled"; 185 }; 186 187 rkcif_mipi_lvds1_sditf: rkcif-mipi-lvds1-sditf { 188 compatible = "rockchip,rkcif-sditf"; 189 rockchip,cif = <&rkcif_mipi_lvds1>; 190 status = "disabled"; 191 }; 192 193 rkdvbm: rkdvbm { 194 compatible = "rockchip,rk-dvbm"; 195 status = "disabled"; 196 }; 197 198 rkisp_vir0: rkisp-vir0 { 199 compatible = "rockchip,rkisp-vir"; 200 rockchip,hw = <&rkisp>; 201 dvbm = <&rkdvbm>; 202 status = "disabled"; 203 }; 204 205 rkisp_vir1: rkisp-vir1 { 206 compatible = "rockchip,rkisp-vir"; 207 rockchip,hw = <&rkisp>; 208 dvbm = <&rkdvbm>; 209 status = "disabled"; 210 }; 211 212 thermal_zones: thermal-zones { 213 soc_thermal: soc-thermal { 214 polling-delay-passive = <20>; /* milliseconds */ 215 polling-delay = <1000>; /* milliseconds */ 216 thermal-sensors = <&tsadc 0>; 217 trips { 218 soc_crit: soc-crit { 219 /* millicelsius */ 220 temperature = <115000>; 221 /* millicelsius */ 222 hysteresis = <2000>; 223 type = "critical"; 224 }; 225 }; 226 }; 227 }; 228 229 timer { 230 compatible = "arm,armv7-timer"; 231 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>, 232 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 233 clock-frequency = <24000000>; 234 }; 235 236 cru: clock-controller@20000000 { 237 compatible = "rockchip,rv1103b-cru"; 238 reg = <0x20000000 0x81000>; 239 #clock-cells = <1>; 240 #reset-cells = <1>; 241 242 assigned-clocks = 243 <&cru PLL_GPLL>, <&cru CLK_GPLL_DIV12>; 244 assigned-clock-rates = 245 <1188000000>, <100000000>; 246 }; 247 248 /* 249 * Merge all GRF, each independent GRF offset is shown as bellow: 250 * VEPU_GRF: 0x20100000 251 * NPU_GRF: 0x20110000 252 * VI_GRF: 0x20120000 253 * CPU_GRF: 0x20130000 254 * DDR_GRF: 0x20140000 255 * SYS_GRF: 0x20150000 256 * PMU_GRF: 0x20160000 257 */ 258 grf: syscon@20100000 { 259 compatible = "rockchip,rv1103b-grf", "syscon", "simple-mfd"; 260 reg = <0x20100000 0x61000>; 261 262 reboot_mode: reboot-mode { 263 compatible = "syscon-reboot-mode"; 264 offset = <0x60200>; 265 mode-bootloader = <BOOT_BL_DOWNLOAD>; 266 mode-charge = <BOOT_CHARGING>; 267 mode-fastboot = <BOOT_FASTBOOT>; 268 mode-loader = <BOOT_BL_DOWNLOAD>; 269 mode-normal = <BOOT_NORMAL>; 270 mode-recovery = <BOOT_RECOVERY>; 271 mode-ums = <BOOT_UMS>; 272 mode-panic = <BOOT_PANIC>; 273 mode-watchdog = <BOOT_WATCHDOG>; 274 }; 275 }; 276 277 ioc: syscon@20170000 { 278 compatible = "rockchip,rv1103b-ioc", "syscon"; 279 reg = <0x20170000 0x60000>; 280 }; 281 282 gic: interrupt-controller@20411000 { 283 compatible = "arm,gic-400"; 284 interrupt-controller; 285 #interrupt-cells = <3>; 286 #address-cells = <0>; 287 288 reg = <0x20411000 0x1000>, 289 <0x20412000 0x2000>, 290 <0x20414000 0x2000>, 291 <0x20416000 0x2000>; 292 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 293 }; 294 295 i2c0: i2c@20530000 { 296 compatible = "rockchip,rv1103b-i2c", "rockchip,rk3399-i2c"; 297 reg = <0x20530000 0x1000>; 298 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 299 #address-cells = <1>; 300 #size-cells = <0>; 301 clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>; 302 clock-names = "i2c", "pclk"; 303 pinctrl-names = "default"; 304 pinctrl-0 = <&i2c0m0_xfer_pins>; 305 status = "disabled"; 306 }; 307 308 uart0: serial@20540000 { 309 compatible = "rockchip,rv1103b-uart", "snps,dw-apb-uart"; 310 reg = <0x20540000 0x100>; 311 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 312 reg-shift = <2>; 313 reg-io-width = <4>; 314 dmas = <&dmac 1>, <&dmac 0>; 315 clock-frequency = <24000000>; 316 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; 317 clock-names = "baudclk", "apb_pclk"; 318 pinctrl-names = "default"; 319 pinctrl-0 = <&uart0m0_xfer_pins>; 320 status = "disabled"; 321 }; 322 323 pwm0_4ch_0: pwm@20550000 { 324 compatible = "rockchip,rv1103b-pwm", "rockchip,rk3576-pwm"; 325 reg = <0x20550000 0x1000>; 326 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 327 #pwm-cells = <3>; 328 pinctrl-names = "active"; 329 pinctrl-0 = <&pwm0m0_ch0_pins>; 330 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 331 clock-names = "pwm", "pclk"; 332 status = "disabled"; 333 }; 334 335 pwm0_4ch_1: pwm@20551000 { 336 compatible = "rockchip,rv1103b-pwm", "rockchip,rk3576-pwm"; 337 reg = <0x20551000 0x1000>; 338 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 339 #pwm-cells = <3>; 340 pinctrl-names = "active"; 341 pinctrl-0 = <&pwm0m0_ch1_pins>; 342 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 343 clock-names = "pwm", "pclk"; 344 status = "disabled"; 345 }; 346 347 pwm0_4ch_2: pwm@20552000 { 348 compatible = "rockchip,rv1103b-pwm", "rockchip,rk3576-pwm"; 349 reg = <0x20552000 0x1000>; 350 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 351 #pwm-cells = <3>; 352 pinctrl-names = "active"; 353 pinctrl-0 = <&pwm0m0_ch2_pins>; 354 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 355 clock-names = "pwm", "pclk"; 356 status = "disabled"; 357 }; 358 359 pwm0_4ch_3: pwm@20553000 { 360 compatible = "rockchip,rv1103b-pwm", "rockchip,rk3576-pwm"; 361 reg = <0x20553000 0x1000>; 362 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 363 #pwm-cells = <3>; 364 pinctrl-names = "active"; 365 pinctrl-0 = <&pwm0m0_ch3_pins>; 366 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>; 367 clock-names = "pwm", "pclk"; 368 status = "disabled"; 369 }; 370 371 lpmcu_mbox0: mailbox@20580000 { 372 compatible = "rockchip,rv1103b-mailbox", "rockchip,rk3576-mailbox"; 373 reg = <0x20580000 0x20>; 374 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 375 clocks = <&cru PCLK_LPMCU_MAILBOX>; 376 clock-names = "pclk_mailbox"; 377 #mbox-cells = <1>; 378 status = "disabled"; 379 }; 380 381 lpmcu_mbox1: mailbox@20581000 { 382 compatible = "rockchip,rv1103b-mailbox", "rockchip,rk3576-mailbox"; 383 reg = <0x20581000 0x20>; 384 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 385 clocks = <&cru PCLK_LPMCU_MAILBOX>; 386 clock-names = "pclk_mailbox"; 387 #mbox-cells = <1>; 388 status = "disabled"; 389 }; 390 391 lpmcu_mbox2: mailbox@20582000 { 392 compatible = "rockchip,rv1103b-mailbox", "rockchip,rk3576-mailbox"; 393 reg = <0x20582000 0x20>; 394 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&cru PCLK_LPMCU_MAILBOX>; 396 clock-names = "pclk_mailbox"; 397 #mbox-cells = <1>; 398 status = "disabled"; 399 }; 400 401 lpmcu_mbox3: mailbox@20583000 { 402 compatible = "rockchip,rv1103b-mailbox", "rockchip,rk3576-mailbox"; 403 reg = <0x20583000 0x20>; 404 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 405 clocks = <&cru PCLK_LPMCU_MAILBOX>; 406 clock-names = "pclk_mailbox"; 407 #mbox-cells = <1>; 408 status = "disabled"; 409 }; 410 411 rga2: rga@20640000 { 412 compatible = "rockchip,rga2"; 413 reg = <0x20640000 0x1000>; 414 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 415 interrupt-names = "rga2_irq"; 416 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_CORE_RGA>; 417 clock-names = "aclk_rga", "hclk_rga", "clk_rga"; 418 status = "disabled"; 419 }; 420 421 sdmmc1: mmc@20650000 { 422 compatible = "rockchip,rv1103b-dw-mshc", "rockchip,rk3288-dw-mshc"; 423 reg = <0x20650000 0x4000>; 424 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 425 clocks = <&cru HCLK_SDMMC1>, <&cru CCLK_SDMMC1>; 426 clock-names = "biu", "ciu"; 427 fifo-depth = <0x100>; 428 max-frequency = <150000000>; 429 pinctrl-names = "default"; 430 pinctrl-0 = <&sdmmc1_clk_pins &sdmmc1_cmd_pins &sdmmc1_bus4_pins>; 431 status = "disabled"; 432 }; 433 434 sai: sai@20660000 { 435 compatible = "rockchip,rv1103b-sai", "rockchip,sai-v1"; 436 reg = <0x20660000 0x1000>; 437 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 438 clocks = <&cru MCLK_SAI>, <&cru HCLK_SAI>; 439 clock-names = "mclk", "hclk"; 440 dmas = <&dmac 11>, <&dmac 10>; 441 dma-names = "tx", "rx"; 442 resets = <&cru SRST_MRESETN_SAI>, <&cru SRST_HRESETN_SAI>; 443 reset-names = "m", "h"; 444 #sound-dai-cells = <0>; 445 sound-name-prefix = "SAI"; 446 status = "disabled"; 447 }; 448 449 crypto: crypto@20680000 { 450 compatible = "rockchip,crypto-v4"; 451 reg = <0x20680000 0x2000>; 452 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 453 clocks = <&cru ACLK_CRYPTO>, <&cru HCLK_CRYPTO>, 454 <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>; 455 clock-names = "aclk", "hclk", "sclk", "pka"; 456 assigned-clocks = <&cru CLK_CORE_CRYPTO>, <&cru CLK_PKA_CRYPTO>; 457 assigned-clock-rates = <300000000>, <300000000>; 458 resets = <&cru SRST_RESETN_CORE_CRYPTO>; 459 reset-names = "crypto-rst"; 460 status = "disabled"; 461 }; 462 463 rng: rng@20690000 { 464 compatible = "rockchip,rkrng"; 465 reg = <0x20690000 0x200>; 466 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 467 clocks = <&cru HCLK_RK_RNG_NS>; 468 clock-names = "hclk_trng"; 469 resets = <&cru SRST_HRESETN_RK_RNG_NS>; 470 reset-names = "reset"; 471 status = "disabled"; 472 }; 473 474 hwlock: hwspinlock@20700000 { 475 compatible = "rockchip,hwspinlock"; 476 reg = <0x20700000 0x100>; 477 #hwlock-cells = <1>; 478 rockchip,hwlock-num-locks = <64>; 479 status = "disabled"; 480 }; 481 482 dmac: dma-controller@20740000 { 483 compatible = "rockchip,rv1103b-dma", "rockchip,dma"; 484 reg = <0x20740000 0x2000>; 485 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 486 clocks = <&cru ACLK_RKDMA>; 487 clock-names = "aclk"; 488 #dma-cells = <1>; 489 }; 490 491 rtc: rtc@20750000 { 492 compatible = "rockchip,rv1103b-rtc"; 493 reg = <0x20750000 0x1000>; 494 rockchip,grf = <&grf>; 495 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 496 clocks = <&cru PCLK_RTC_ROOT>; 497 clock-names = "pclk_phy"; 498 assigned-clocks = <&cru PCLK_RTC_ROOT>; 499 assigned-clock-rates = <50000000>; 500 status = "disabled"; 501 }; 502 503 gmac: ethernet@20800000 { 504 compatible = "rockchip,rv1103b-gmac", "snps,dwmac-4.20a"; 505 reg = <0x20800000 0x10000>; 506 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 508 interrupt-names = "macirq", "eth_wake_irq"; 509 rockchip,grf = <&grf>; 510 clocks = <&cru ACLK_MAC>, <&cru PCLK_MAC>; 511 clock-names = "aclk_mac", "pclk_mac"; 512 resets = <&cru SRST_ARESETN_MAC>; 513 reset-names = "stmmaceth"; 514 515 snps,mixed-burst; 516 snps,tso; 517 518 tx-dma-size = <256>; 519 rx-dma-size = <128>; 520 521 snps,axi-config = <&stmmac_axi_setup>; 522 snps,mtl-rx-config = <&mtl_rx_setup>; 523 snps,mtl-tx-config = <&mtl_tx_setup>; 524 525 phy-mode = "rmii"; 526 clock_in_out = "input"; 527 phy-handle = <&rmii_phy>; 528 529 /* FLOW_OFF: 0, FLOW_RX: 1, FLOW_TX: 2, FLOW_AUTO: 3 */ 530 snps,flow-ctrl = <0>; 531 532 nvmem-cells = <&macphy_bgs>; 533 nvmem-cell-names = "bgs"; 534 status = "disabled"; 535 536 mdio: mdio { 537 compatible = "snps,dwmac-mdio"; 538 #address-cells = <0x1>; 539 #size-cells = <0x0>; 540 rmii_phy: ethernet-phy@2 { 541 compatible = "ethernet-phy-id0044.1400", "ethernet-phy-ieee802.3-c22"; 542 reg = <2>; 543 clocks = <&cru CLK_MACPHY>; 544 resets = <&cru SRST_RESETN_MACPHY>; 545 phy-is-integrated; 546 nvmem-cells = <&macphy_txlevel>; 547 nvmem-cell-names = "txlevel"; 548 bgs,increment = <2>; 549 rockchip,thermal-zone = "soc-thermal"; 550 }; 551 }; 552 553 stmmac_axi_setup: stmmac-axi-config { 554 snps,wr_osr_lmt = <4>; 555 snps,rd_osr_lmt = <8>; 556 snps,blen = <0 0 0 0 16 8 4>; 557 }; 558 559 mtl_rx_setup: rx-queues-config { 560 snps,rx-queues-to-use = <1>; 561 queue0 { 562 status = "okay"; 563 }; 564 }; 565 566 mtl_tx_setup: tx-queues-config { 567 snps,tx-queues-to-use = <1>; 568 queue0 { 569 status = "okay"; 570 }; 571 }; 572 }; 573 574 otp: otp@20820000 { 575 compatible = "rockchip,rv1103b-otp"; 576 reg = <0x20820000 0x4000>; 577 #address-cells = <1>; 578 #size-cells = <1>; 579 580 clocks = <&cru CLK_USER_OTPC_NS>, <&cru CLK_SBPI_OTPC_NS>, 581 <&cru PCLK_OTPC_NS>, <&cru PCLK_OTP_MASK>, 582 <&cru CLK_OTPC_ARB>; 583 clock-names = "usr", "sbpi", "apb", "phy", "arb"; 584 resets = <&cru SRST_RESETN_USER_OTPC_NS>, <&cru SRST_RESETN_SBPI_OTPC_NS>, 585 <&cru SRST_PRESETN_OTPC_NS>, <&cru SRST_PRESETN_OTP_MASK>, 586 <&cru SRST_RESETN_OTPC_ARB>; 587 reset-names = "usr", "sbpi", "apb", "phy", "arb"; 588 589 /* Data cells */ 590 cpu_code: cpu-code@2 { 591 reg = <0x02 0x2>; 592 }; 593 otp_cpu_version: cpu-version@8 { 594 reg = <0x08 0x1>; 595 bits = <3 3>; 596 }; 597 otp_id: id@a { 598 reg = <0x0a 0x10>; 599 }; 600 cpu_leakage: cpu-leakage@1a { 601 reg = <0x1a 0x1>; 602 }; 603 log_leakage: log-leakage@1b { 604 reg = <0x1b 0x1>; 605 }; 606 macphy_bgs: macphy-bgs@2d { 607 reg = <0x2d 0x1>; 608 }; 609 macphy_txlevel: macphy-txlevel@2e { 610 reg = <0x2e 0x2>; 611 }; 612 }; 613 614 spi0: spi@20850000 { 615 compatible = "rockchip,rv1103b-spi", "rockchip,rk3066-spi"; 616 reg = <0x20850000 0x1000>; 617 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 618 #address-cells = <1>; 619 #size-cells = <0>; 620 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>; 621 clock-names = "spiclk", "apb_pclk"; 622 dmas = <&dmac 15>, <&dmac 14>; 623 dma-names = "tx", "rx"; 624 pinctrl-names = "default"; 625 pinctrl-0 = <&spi0m0_cs0_pins &spi0m0_cs1_pins &spi0m0_clk_pins>; 626 status = "disabled"; 627 }; 628 629 uart1: serial@20870000 { 630 compatible = "rockchip,rv1103b-uart", "snps,dw-apb-uart"; 631 reg = <0x20870000 0x100>; 632 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 633 reg-shift = <2>; 634 reg-io-width = <4>; 635 dmas = <&dmac 3>, <&dmac 2>; 636 clock-frequency = <24000000>; 637 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 638 clock-names = "baudclk", "apb_pclk"; 639 pinctrl-names = "default"; 640 pinctrl-0 = <&uart1m0_xfer_pins>; 641 status = "disabled"; 642 }; 643 644 uart2: serial@20880000 { 645 compatible = "rockchip,rv1103b-uart", "snps,dw-apb-uart"; 646 reg = <0x20880000 0x100>; 647 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 648 reg-shift = <2>; 649 reg-io-width = <4>; 650 dmas = <&dmac 5>, <&dmac 4>; 651 clock-frequency = <24000000>; 652 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 653 clock-names = "baudclk", "apb_pclk"; 654 pinctrl-names = "default"; 655 pinctrl-0 = <&uart2m0_xfer_pins>; 656 status = "disabled"; 657 }; 658 659 wdt: watchdog@208d0000 { 660 compatible = "snps,dw-wdt"; 661 reg = <0x208d0000 0x100>; 662 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>; 663 clock-names = "tclk", "pclk"; 664 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 665 status = "disabled"; 666 }; 667 668 i2c1: i2c@20910000 { 669 compatible = "rockchip,rv1103b-i2c", "rockchip,rk3399-i2c"; 670 reg = <0x20910000 0x1000>; 671 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 672 #address-cells = <1>; 673 #size-cells = <0>; 674 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>; 675 clock-names = "i2c", "pclk"; 676 pinctrl-names = "default"; 677 pinctrl-0 = <&i2c1m0_xfer_pins>; 678 status = "disabled"; 679 }; 680 681 i2c2: i2c@20920000 { 682 compatible = "rockchip,rv1103b-i2c", "rockchip,rk3399-i2c"; 683 reg = <0x20920000 0x1000>; 684 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 685 #address-cells = <1>; 686 #size-cells = <0>; 687 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>; 688 clock-names = "i2c", "pclk"; 689 pinctrl-names = "default"; 690 pinctrl-0 = <&i2c2m0_xfer_pins>; 691 status = "disabled"; 692 }; 693 694 i2c3: i2c@20930000 { 695 compatible = "rockchip,rv1103b-i2c", "rockchip,rk3399-i2c"; 696 reg = <0x20930000 0x1000>; 697 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 698 #address-cells = <1>; 699 #size-cells = <0>; 700 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>; 701 clock-names = "i2c", "pclk"; 702 pinctrl-names = "default"; 703 pinctrl-0 = <&i2c3m0_xfer_pins>; 704 status = "disabled"; 705 }; 706 707 i2c4: i2c@20940000 { 708 compatible = "rockchip,rv1103b-i2c", "rockchip,rk3399-i2c"; 709 reg = <0x20940000 0x1000>; 710 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 711 #address-cells = <1>; 712 #size-cells = <0>; 713 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>; 714 clock-names = "i2c", "pclk"; 715 pinctrl-names = "default"; 716 pinctrl-0 = <&i2c4m0_xfer_pins>; 717 status = "disabled"; 718 }; 719 720 pwm1_4ch_0: pwm@20970000 { 721 compatible = "rockchip,rv1103b-pwm", "rockchip,rk3576-pwm"; 722 reg = <0x20970000 0x1000>; 723 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 724 #pwm-cells = <3>; 725 pinctrl-names = "active"; 726 pinctrl-0 = <&pwm1m0_ch0_pins>; 727 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 728 clock-names = "pwm", "pclk"; 729 status = "disabled"; 730 }; 731 732 pwm1_4ch_1: pwm@20971000 { 733 compatible = "rockchip,rv1103b-pwm", "rockchip,rk3576-pwm"; 734 reg = <0x20971000 0x1000>; 735 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 736 #pwm-cells = <3>; 737 pinctrl-names = "active"; 738 pinctrl-0 = <&pwm1m0_ch1_pins>; 739 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 740 clock-names = "pwm", "pclk"; 741 status = "disabled"; 742 }; 743 744 pwm1_4ch_2: pwm@20972000 { 745 compatible = "rockchip,rv1103b-pwm", "rockchip,rk3576-pwm"; 746 reg = <0x20972000 0x1000>; 747 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 748 #pwm-cells = <3>; 749 pinctrl-names = "active"; 750 pinctrl-0 = <&pwm1m0_ch2_pins>; 751 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 752 clock-names = "pwm", "pclk"; 753 status = "disabled"; 754 }; 755 756 pwm1_4ch_3: pwm@20973000 { 757 compatible = "rockchip,rv1103b-pwm", "rockchip,rk3576-pwm"; 758 reg = <0x20973000 0x1000>; 759 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 760 #pwm-cells = <3>; 761 pinctrl-names = "active"; 762 pinctrl-0 = <&pwm1m0_ch3_pins>; 763 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>; 764 clock-names = "pwm", "pclk"; 765 status = "disabled"; 766 }; 767 768 pwm2_4ch_0: pwm@20980000 { 769 compatible = "rockchip,rv1103b-pwm", "rockchip,rk3576-pwm"; 770 reg = <0x20980000 0x1000>; 771 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 772 #pwm-cells = <3>; 773 pinctrl-names = "active"; 774 pinctrl-0 = <&pwm2m0_ch0_pins>; 775 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 776 clock-names = "pwm", "pclk"; 777 status = "disabled"; 778 }; 779 780 pwm2_4ch_1: pwm@20981000 { 781 compatible = "rockchip,rv1103b-pwm", "rockchip,rk3576-pwm"; 782 reg = <0x20981000 0x1000>; 783 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 784 #pwm-cells = <3>; 785 pinctrl-names = "active"; 786 pinctrl-0 = <&pwm2m0_ch1_pins>; 787 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 788 clock-names = "pwm", "pclk"; 789 status = "disabled"; 790 }; 791 792 pwm2_4ch_2: pwm@20982000 { 793 compatible = "rockchip,rv1103b-pwm", "rockchip,rk3576-pwm"; 794 reg = <0x20982000 0x1000>; 795 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 796 #pwm-cells = <3>; 797 pinctrl-names = "active"; 798 pinctrl-0 = <&pwm2m0_ch2_pins>; 799 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 800 clock-names = "pwm", "pclk"; 801 status = "disabled"; 802 }; 803 804 pwm2_4ch_3: pwm@20983000 { 805 compatible = "rockchip,rv1103b-pwm", "rockchip,rk3576-pwm"; 806 reg = <0x20983000 0x1000>; 807 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 808 #pwm-cells = <3>; 809 pinctrl-names = "active"; 810 pinctrl-0 = <&pwm2m0_ch3_pins>; 811 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>; 812 clock-names = "pwm", "pclk"; 813 status = "disabled"; 814 }; 815 816 saradc: adc@209a0000 { 817 compatible = "rockchip,rv1103b-saradc", "rockchip,rk3588-saradc"; 818 reg = <0x209a0000 0x10000>; 819 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 820 #io-channel-cells = <1>; 821 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; 822 clock-names = "saradc", "apb_pclk"; 823 resets = <&cru SRST_PRESETN_SARADC>; 824 reset-names = "saradc-apb"; 825 status = "disabled"; 826 }; 827 828 tsadc: tsadc@209b0000 { 829 compatible = "rockchip,rv1103b-tsadc"; 830 reg = <0x209b0000 0x400>; 831 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 832 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>, <&cru CLK_TSADC_TSEN>; 833 clock-names = "tsadc", "apb_pclk", "tsen"; 834 assigned-clocks = <&cru CLK_TSADC>, <&cru CLK_TSADC_TSEN>; 835 assigned-clock-rates = <1000000>, <12000000>; 836 resets = <&cru SRST_RESETN_TSADC>, <&cru SRST_PRESETN_TSADC>; 837 reset-names = "tsadc", "tsadc-apb"; 838 #thermal-sensor-cells = <1>; 839 rockchip,grf = <&grf>; 840 rockchip,hw-tshut-temp = <120000>; 841 rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */ 842 rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */ 843 status = "disabled"; 844 }; 845 846 hw_decompress: decompress@209f0000 { 847 compatible = "rockchip,hw-decompress"; 848 reg = <0x209f0000 0x1000>; 849 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 850 clocks = <&cru ACLK_DECOM>, <&cru DCLK_DECOM>, <&cru PCLK_DECOM>; 851 clock-names = "aclk", "dclk", "pclk"; 852 resets = <&cru SRST_DRESETN_DECOM>; 853 reset-names = "dresetn"; 854 status = "disabled"; 855 }; 856 857 hpmcu_mbox0: mailbox@20a10000 { 858 compatible = "rockchip,rv1103b-mailbox", "rockchip,rk3576-mailbox"; 859 reg = <0x20a10000 0x20>; 860 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 861 clocks = <&cru PCLK_HPMCU_MAILBOX>; 862 clock-names = "pclk_mailbox"; 863 #mbox-cells = <1>; 864 status = "disabled"; 865 }; 866 867 hpmcu_mbox1: mailbox@20a11000 { 868 compatible = "rockchip,rv1103b-mailbox", "rockchip,rk3576-mailbox"; 869 reg = <0x20a11000 0x20>; 870 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 871 clocks = <&cru PCLK_HPMCU_MAILBOX>; 872 clock-names = "pclk_mailbox"; 873 #mbox-cells = <1>; 874 status = "disabled"; 875 }; 876 877 hpmcu_mbox2: mailbox@20a12000 { 878 compatible = "rockchip,rv1103b-mailbox", "rockchip,rk3576-mailbox"; 879 reg = <0x20a12000 0x20>; 880 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 881 clocks = <&cru PCLK_HPMCU_MAILBOX>; 882 clock-names = "pclk_mailbox"; 883 #mbox-cells = <1>; 884 status = "disabled"; 885 }; 886 887 hpmcu_mbox3: mailbox@20a13000 { 888 compatible = "rockchip,rv1103b-mailbox", "rockchip,rk3576-mailbox"; 889 reg = <0x20a13000 0x20>; 890 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 891 clocks = <&cru PCLK_HPMCU_MAILBOX>; 892 clock-names = "pclk_mailbox"; 893 #mbox-cells = <1>; 894 status = "disabled"; 895 }; 896 897 usbdrd: usbdrd { 898 compatible = "rockchip,rv1103b-dwc3", "rockchip,rk3399-dwc3"; 899 clocks = <&cru CLK_REF_USBOTG>, <&cru CLK_UTMI_USBOTG>, 900 <&cru ACLK_USBOTG>; 901 clock-names = "ref", "utmi", "bus"; 902 #address-cells = <1>; 903 #size-cells = <1>; 904 ranges; 905 status = "disabled"; 906 907 usbdrd_dwc3: usb@20b00000 { 908 compatible = "snps,dwc3"; 909 reg = <0x20b00000 0x100000>; 910 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 911 resets = <&cru SRST_ARESETN_USBOTG>; 912 reset-names = "usb3-otg"; 913 dr_mode = "otg"; 914 maximum-speed = "high-speed"; 915 phys = <&u2phy_otg>; 916 phy-names = "usb2-phy"; 917 phy_type = "utmi_wide"; 918 snps,dis_enblslpm_quirk; 919 snps,dis-u2-freeclk-exists-quirk; 920 snps,dis_u2_susphy_quirk; 921 snps,dis-del-phy-power-chg-quirk; 922 snps,dis-tx-ipgap-linecheck-quirk; 923 snps,usb2-gadget-lpm-disable; 924 snps,usb2-lpm-disable; 925 snps,parkmode-disable-hs-quirk; 926 status = "disabled"; 927 }; 928 }; 929 930 rkisp: rkisp@20d00000 { 931 compatible = "rockchip,rv1103b-rkisp"; 932 reg = <0x20d00000 0x7f00>; 933 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 936 interrupt-names = "mipi_irq", "mi_irq", "isp_irq"; 937 clocks = <&cru ACLK_ISP>, <&cru HCLK_ISP>, 938 <&cru CLK_CORE_ISP>, <&cru ISP0CLK_VICAP>; 939 clock-names = "aclk_isp", "hclk_isp", 940 "clk_isp_core", "clk_isp_core_vicap"; 941 status = "disabled"; 942 }; 943 944 rkcif: rkcif@20d10000 { 945 compatible = "rockchip,rv1103b-cif"; 946 reg = <0x20d10000 0x10000>; 947 reg-names = "cif_regs"; 948 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 949 interrupt-names = "cif-intr"; 950 clocks = <&cru ACLK_VICAP>, <&cru HCLK_VICAP>, 951 <&cru DCLK_VICAP>, <&cru ISP0CLK_VICAP>; 952 clock-names = "aclk_cif", "hclk_cif", 953 "dclk_cif", "isp0clk_cif"; 954 resets = <&cru SRST_ARESETN_VICAP>, <&cru SRST_HRESETN_VICAP>, 955 <&cru SRST_DRESETN_VICAP>, <&cru SRST_ISP0RESETN_VICAP>; 956 reset-names = "rst_cif_a", "rst_cif_h", 957 "rst_cif_d", "rst_cif_isp0"; 958 rockchip,grf = <&grf>; 959 status = "disabled"; 960 }; 961 962 sdmmc0: mmc@20d20000 { 963 compatible = "rockchip,rv1103b-dw-mshc", "rockchip,rk3288-dw-mshc"; 964 reg = <0x20d20000 0x4000>; 965 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 966 clocks = <&cru HCLK_SDMMC0>, <&cru CCLK_SDMMC0>; 967 clock-names = "biu", "ciu"; 968 fifo-depth = <0x100>; 969 max-frequency = <150000000>; 970 pinctrl-names = "normal", "idle"; 971 pinctrl-0 = <&sdmmc0_clk_pins &sdmmc0_cmd_pins &sdmmc0_det_pins &sdmmc0_bus4_pins>; 972 pinctrl-1 = <&sdmmc0_idle_pins &sdmmc0_det_pins>; 973 status = "disabled"; 974 }; 975 976 emmc: mmc@20d30000 { 977 compatible = "rockchip,rv1103b-dw-mshc", "rockchip,rk3288-dw-mshc"; 978 reg = <0x20d30000 0x4000>; 979 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 980 clocks = <&cru HCLK_EMMC>, <&cru CCLK_EMMC>; 981 clock-names = "biu", "ciu"; 982 fifo-depth = <0x100>; 983 max-frequency = <150000000>; 984 status = "disabled"; 985 }; 986 987 sfc: spi@20d40000 { 988 compatible = "rockchip,fspi"; 989 reg = <0x20d40000 0x4000>; 990 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 991 clocks = <&cru SCLK_SFC_2X>, <&cru HCLK_SFC>; 992 clock-names = "clk_sfc", "hclk_sfc"; 993 rockchip,max-dll = <0xFF>; 994 rockchip,sclk-x2-bypass; 995 #address-cells = <1>; 996 #size-cells = <0>; 997 status = "disabled"; 998 }; 999 1000 mipi0_csi2_hw: mipi-csi2-hw@20d90000 { 1001 compatible = "rockchip,rv1103b-mipi-csi2-hw"; 1002 reg = <0x20d90000 0x10000>; 1003 reg-names = "csihost_regs"; 1004 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1005 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1006 interrupt-names = "csi-intr1", "csi-intr2"; 1007 clocks = <&cru PCLK_CSI2HOST0>; 1008 clock-names = "pclk_csi2host"; 1009 resets = <&cru SRST_PRESETN_CSI2HOST0>; 1010 reset-names = "srst_csihost_p"; 1011 status = "okay"; 1012 }; 1013 1014 mipi1_csi2_hw: mipi-csi2-hw@20da0000 { 1015 compatible = "rockchip,rv1103b-mipi-csi2-hw"; 1016 reg = <0x20da0000 0x10000>; 1017 reg-names = "csihost_regs"; 1018 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1019 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1020 interrupt-names = "csi-intr1", "csi-intr2"; 1021 clocks = <&cru PCLK_CSI2HOST1>; 1022 clock-names = "pclk_csi2host"; 1023 resets = <&cru SRST_PRESETN_CSI2HOST1>; 1024 reset-names = "srst_csihost_p"; 1025 status = "okay"; 1026 }; 1027 1028 csi2_dphy_hw: csi2-dphy-hw@20db0000 { 1029 compatible = "rockchip,rv1103b-csi2-dphy-hw"; 1030 reg = <0x20db0000 0x8000>; 1031 clocks = <&cru PCLK_CSIPHY>; 1032 clock-names = "pclk"; 1033 resets = <&cru SRST_PRESETN_CSIPHY>; 1034 reset-names = "srst_p_csiphy"; 1035 rockchip,grf = <&grf>; 1036 status = "disabled"; 1037 }; 1038 1039 u2phy: usb2-phy@20e10000 { 1040 compatible = "rockchip,rv1103b-usb2phy"; 1041 reg = <0x20e10000 0x8000>; 1042 clocks = <&cru CLK_REF_USBPHY>, <&cru PCLK_USBPHY>; 1043 clock-names = "phyclk", "pclk"; 1044 resets = <&cru SRST_RESETN_USBPHY_POR>, <&cru SRST_RESETN_USBPHY_OTG>; 1045 reset-names = "u2phy", "u2phy-apb"; 1046 rockchip,usbgrf = <&grf>; 1047 #clock-cells = <0>; 1048 status = "disabled"; 1049 1050 u2phy_otg: otg-port { 1051 #phy-cells = <0>; 1052 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1053 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1054 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1055 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 1056 interrupt-names = "otg-bvalid", "otg-id", 1057 "linestate", "disconnect"; 1058 status = "disabled"; 1059 }; 1060 }; 1061 1062 acodec: acodec@20e20000 { 1063 compatible = "rockchip,rv1103b-codec"; 1064 reg = <0x20e20000 0x1000>; 1065 rockchip,grf = <&grf>; 1066 clocks = <&cru PCLK_ACODEC>, 1067 <&cru MCLK_ACODEC_TX>, 1068 <&cru MCLK_SAI>; 1069 clock-names = "pclk_acodec", "mclk_acodec", "mclk_cpu"; 1070 resets = <&cru SRST_PRESETN_ACODEC>; 1071 reset-names = "acodec-reset"; 1072 acodec,micbias; 1073 acodec,inner-i2s; 1074 init-mic-gain = <0x22>; /* Left:20dB Right:20dB */ 1075 #sound-dai-cells = <0>; 1076 status = "disabled"; 1077 }; 1078 1079 rkvenc: rkvenc@20e80000 { 1080 compatible = "rockchip,rkv-encoder-rv1103b"; 1081 reg = <0x20e80000 0x6000>; 1082 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1083 interrupt-names = "irq_rkvenc"; 1084 clocks = <&cru ACLK_VEPU>, <&cru HCLK_VEPU>, <&cru CLK_CORE_VEPU>; 1085 clock-names = "aclk_vcodec", "hclk_vcodec", "clk_core"; 1086 rockchip,normal-rates = <400000000>, <0>, <400000000>; 1087 assigned-clocks = <&cru ACLK_VEPU>, <&cru CLK_CORE_VEPU>; 1088 assigned-clock-rates = <400000000>, <400000000>; 1089 resets = <&cru SRST_ARESETN_VEPU>, <&cru SRST_HRESETN_VEPU>, 1090 <&cru SRST_RESETN_CORE_VEPU>; 1091 reset-names = "video_a", "video_h", "video_core"; 1092 rockchip,srv = <&mpp_srv>; 1093 rockchip,taskqueue-node = <0>; 1094 dvbm = <&rkdvbm>; 1095 status = "disabled"; 1096 }; 1097 1098 system_sram: sram@210f6000 { 1099 compatible = "mmio-sram"; 1100 reg = <0x210f6000 0x8000>; 1101 #address-cells = <1>; 1102 #size-cells = <1>; 1103 ranges = <0 0x210f6000 0x8000>; 1104 }; 1105 1106 pinctrl: pinctrl { 1107 compatible = "rockchip,rv1103b-pinctrl"; 1108 rockchip,grf = <&ioc>; 1109 #address-cells = <1>; 1110 #size-cells = <1>; 1111 ranges; 1112 1113 gpio0: gpio@20520000 { 1114 compatible = "rockchip,gpio-bank"; 1115 reg = <0x20520000 0x200>; 1116 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1117 clocks = <&cru PCLK_PMU_GPIO0>, <&cru DBCLK_PMU_GPIO0>; 1118 gpio-controller; 1119 #gpio-cells = <2>; 1120 gpio-ranges = <&pinctrl 0 0 32>; 1121 interrupt-controller; 1122 #interrupt-cells = <2>; 1123 }; 1124 1125 gpio1: gpio@20d80000 { 1126 compatible = "rockchip,gpio-bank"; 1127 reg = <0x20d80000 0x200>; 1128 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 1129 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; 1130 gpio-controller; 1131 #gpio-cells = <2>; 1132 gpio-ranges = <&pinctrl 0 32 32>; 1133 interrupt-controller; 1134 #interrupt-cells = <2>; 1135 }; 1136 1137 gpio2: gpio@20840000 { 1138 compatible = "rockchip,gpio-bank"; 1139 reg = <0x20840000 0x200>; 1140 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1141 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; 1142 gpio-controller; 1143 #gpio-cells = <2>; 1144 gpio-ranges = <&pinctrl 0 64 32>; 1145 interrupt-controller; 1146 #interrupt-cells = <2>; 1147 }; 1148 }; 1149}; 1150 1151#include "rv1103b-pinctrl.dtsi" 1152